📄 cnt500.rpt
字号:
Device-Specific Information: e:\edashi\sin\cnt500.rpt
cnt500
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - F 01 DFFE 0 2 0 2 |7490:9|QB (|7490:9|:11)
- 3 - F 01 DFFE 0 2 0 1 |7490:9|QC (|7490:9|:14)
- 4 - F 01 DFFE 0 3 1 1 |7490:9|QD (|7490:9|:19)
- 2 - F 17 DFFE 0 1 0 3 |7490:10|QA (|7490:10|:7)
- 2 - F 01 DFFE 0 2 0 2 |7490:10|QB (|7490:10|:11)
- 1 - F 01 DFFE 0 2 0 1 |7490:10|QC (|7490:10|:14)
- 6 - F 01 DFFE 0 3 0 4 |7490:10|QD (|7490:10|:19)
- 1 - F 09 DFFE + 0 0 0 3 |7490:11|QA (|7490:11|:7)
- 3 - F 17 DFFE 0 2 0 2 |7490:11|QB (|7490:11|:11)
- 1 - F 17 DFFE 0 2 0 1 |7490:11|QC (|7490:11|:14)
- 4 - F 17 DFFE 0 3 0 2 |7490:11|QD (|7490:11|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\edashi\sin\cnt500.rpt
cnt500
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 1/144( 0%) 2/ 72( 2%) 0/ 72( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\edashi\sin\cnt500.rpt
cnt500
** CLOCK SIGNALS **
Type Fan-out Name
DFF 4 |7490:10|QA
DFF 4 |7490:10|QD
DFF 4 |7490:11|QA
DFF 2 |7490:11|QD
INPUT 1 clk5m
Device-Specific Information: e:\edashi\sin\cnt500.rpt
cnt500
** EQUATIONS **
clk5m : INPUT;
-- Node name is 'clk10k'
-- Equation name is 'clk10k', type is output
clk10k = _LC4_F1;
-- Node name is '|7490:9|:11' = '|7490:9|QB'
-- Equation name is '_LC5_F1', type is buried
_LC5_F1 = DFFE( _EQ001, !_LC6_F1, VCC, VCC, VCC);
_EQ001 = !_LC4_F1 & !_LC5_F1;
-- Node name is '|7490:9|:14' = '|7490:9|QC'
-- Equation name is '_LC3_F1', type is buried
_LC3_F1 = DFFE( _EQ002, !_LC6_F1, VCC, VCC, VCC);
_EQ002 = !_LC3_F1 & _LC5_F1
# _LC3_F1 & !_LC5_F1;
-- Node name is '|7490:9|:19' = '|7490:9|QD'
-- Equation name is '_LC4_F1', type is buried
_LC4_F1 = DFFE( _EQ003, !_LC6_F1, VCC, VCC, VCC);
_EQ003 = _LC3_F1 & _LC5_F1;
-- Node name is '|7490:10|:7' = '|7490:10|QA'
-- Equation name is '_LC2_F17', type is buried
_LC2_F17 = DFFE(!_LC2_F17, !_LC4_F17, VCC, VCC, VCC);
-- Node name is '|7490:10|:11' = '|7490:10|QB'
-- Equation name is '_LC2_F1', type is buried
_LC2_F1 = DFFE( _EQ004, !_LC2_F17, VCC, VCC, VCC);
_EQ004 = !_LC2_F1 & !_LC6_F1;
-- Node name is '|7490:10|:14' = '|7490:10|QC'
-- Equation name is '_LC1_F1', type is buried
_LC1_F1 = DFFE( _EQ005, !_LC2_F17, VCC, VCC, VCC);
_EQ005 = !_LC1_F1 & _LC2_F1
# _LC1_F1 & !_LC2_F1;
-- Node name is '|7490:10|:19' = '|7490:10|QD'
-- Equation name is '_LC6_F1', type is buried
_LC6_F1 = DFFE( _EQ006, !_LC2_F17, VCC, VCC, VCC);
_EQ006 = _LC1_F1 & _LC2_F1;
-- Node name is '|7490:11|:7' = '|7490:11|QA'
-- Equation name is '_LC1_F9', type is buried
_LC1_F9 = DFFE(!_LC1_F9, GLOBAL(!clk5m), VCC, VCC, VCC);
-- Node name is '|7490:11|:11' = '|7490:11|QB'
-- Equation name is '_LC3_F17', type is buried
_LC3_F17 = DFFE( _EQ007, !_LC1_F9, VCC, VCC, VCC);
_EQ007 = !_LC3_F17 & !_LC4_F17;
-- Node name is '|7490:11|:14' = '|7490:11|QC'
-- Equation name is '_LC1_F17', type is buried
_LC1_F17 = DFFE( _EQ008, !_LC1_F9, VCC, VCC, VCC);
_EQ008 = !_LC1_F17 & _LC3_F17
# _LC1_F17 & !_LC3_F17;
-- Node name is '|7490:11|:19' = '|7490:11|QD'
-- Equation name is '_LC4_F17', type is buried
_LC4_F17 = DFFE( _EQ009, !_LC1_F9, VCC, VCC, VCC);
_EQ009 = _LC1_F17 & _LC3_F17;
Project Information e:\edashi\sin\cnt500.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10KE' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 37,013K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -