📄 delay.rpt
字号:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 6/ 48( 12%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\sin\delay.rpt
delay
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 42 clk
Device-Specific Information: f:\sin\delay.rpt
delay
** EQUATIONS **
clk : INPUT;
clkin : INPUT;
-- Node name is 'clkout'
-- Equation name is 'clkout', type is output
clkout = _LC8_C20;
-- Node name is ':1'
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = DFFE( clkin, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':5'
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = DFFE( _LC1_C22, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':6'
-- Equation name is '_LC3_C22', type is buried
_LC3_C22 = DFFE( _LC2_C22, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':8'
-- Equation name is '_LC8_C22', type is buried
_LC8_C22 = DFFE( _LC3_C22, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':9'
-- Equation name is '_LC2_C18', type is buried
_LC2_C18 = DFFE( _LC8_C22, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':10'
-- Equation name is '_LC3_C18', type is buried
_LC3_C18 = DFFE( _LC2_C18, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':11'
-- Equation name is '_LC4_C18', type is buried
_LC4_C18 = DFFE( _LC3_C18, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':12'
-- Equation name is '_LC5_C18', type is buried
_LC5_C18 = DFFE( _LC4_C18, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':13'
-- Equation name is '_LC6_C18', type is buried
_LC6_C18 = DFFE( _LC5_C18, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':14'
-- Equation name is '_LC1_C18', type is buried
_LC1_C18 = DFFE( _LC6_C18, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':15'
-- Equation name is '_LC1_C24', type is buried
_LC1_C24 = DFFE( _LC1_C18, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':16'
-- Equation name is '_LC2_C24', type is buried
_LC2_C24 = DFFE( _LC1_C24, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':17'
-- Equation name is '_LC3_C24', type is buried
_LC3_C24 = DFFE( _LC2_C24, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':18'
-- Equation name is '_LC4_C24', type is buried
_LC4_C24 = DFFE( _LC3_C24, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':22'
-- Equation name is '_LC3_C16', type is buried
_LC3_C16 = DFFE( _LC2_C16, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':23'
-- Equation name is '_LC2_C16', type is buried
_LC2_C16 = DFFE( _LC2_C23, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':24'
-- Equation name is '_LC2_C23', type is buried
_LC2_C23 = DFFE( _LC8_C23, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':25'
-- Equation name is '_LC8_C23', type is buried
_LC8_C23 = DFFE( _LC7_C23, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':26'
-- Equation name is '_LC7_C23', type is buried
_LC7_C23 = DFFE( _LC6_C23, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':27'
-- Equation name is '_LC6_C23', type is buried
_LC6_C23 = DFFE( _LC5_C23, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':28'
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = DFFE( _LC4_C23, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':29'
-- Equation name is '_LC4_C23', type is buried
_LC4_C23 = DFFE( _LC3_C23, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':30'
-- Equation name is '_LC3_C23', type is buried
_LC3_C23 = DFFE( _LC1_C23, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':31'
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = DFFE( _LC8_C24, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':32'
-- Equation name is '_LC8_C24', type is buried
_LC8_C24 = DFFE( _LC7_C24, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':33'
-- Equation name is '_LC7_C24', type is buried
_LC7_C24 = DFFE( _LC6_C24, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':34'
-- Equation name is '_LC6_C24', type is buried
_LC6_C24 = DFFE( _LC5_C24, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':35'
-- Equation name is '_LC5_C24', type is buried
_LC5_C24 = DFFE( _LC4_C24, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':38'
-- Equation name is '_LC8_C20', type is buried
_LC8_C20 = DFFE( _LC7_C20, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':39'
-- Equation name is '_LC7_C20', type is buried
_LC7_C20 = DFFE( _LC6_C20, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':40'
-- Equation name is '_LC6_C20', type is buried
_LC6_C20 = DFFE( _LC5_C20, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':41'
-- Equation name is '_LC5_C20', type is buried
_LC5_C20 = DFFE( _LC4_C20, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':42'
-- Equation name is '_LC4_C20', type is buried
_LC4_C20 = DFFE( _LC3_C20, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':43'
-- Equation name is '_LC3_C20', type is buried
_LC3_C20 = DFFE( _LC2_C20, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':44'
-- Equation name is '_LC2_C20', type is buried
_LC2_C20 = DFFE( _LC1_C20, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':45'
-- Equation name is '_LC1_C20', type is buried
_LC1_C20 = DFFE( _LC1_C16, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':46'
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = DFFE( _LC8_C16, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':47'
-- Equation name is '_LC8_C16', type is buried
_LC8_C16 = DFFE( _LC7_C16, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':48'
-- Equation name is '_LC7_C16', type is buried
_LC7_C16 = DFFE( _LC6_C16, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':49'
-- Equation name is '_LC6_C16', type is buried
_LC6_C16 = DFFE( _LC5_C16, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':50'
-- Equation name is '_LC5_C16', type is buried
_LC5_C16 = DFFE( _LC4_C16, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':51'
-- Equation name is '_LC4_C16', type is buried
_LC4_C16 = DFFE( _LC3_C16, GLOBAL( clk), VCC, VCC, VCC);
Project Information f:\sin\delay.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 28,866K
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