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📄 sub8b.rpt

📁 dds信号发生器
💻 RPT
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+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register


Device-Specific Information:                            e:\edashi\am\sub8b.rpt
sub8b

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
B:       1/ 96(  1%)     0/ 48(  0%)     2/ 48(  4%)    0/16(  0%)      3/16( 18%)     0/16(  0%)
C:       7/ 96(  7%)     0/ 48(  0%)     6/ 48( 12%)    6/16( 37%)      3/16( 18%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
16:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
24:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                            e:\edashi\am\sub8b.rpt
sub8b

** EQUATIONS **

suba0    : INPUT;
suba1    : INPUT;
suba2    : INPUT;
suba3    : INPUT;
suba4    : INPUT;
suba5    : INPUT;
suba6    : INPUT;
suba7    : INPUT;
subb0    : INPUT;
subb1    : INPUT;
subb2    : INPUT;
subb3    : INPUT;
subb4    : INPUT;
subb5    : INPUT;
subb6    : INPUT;

-- Node name is 'subn0' 
-- Equation name is 'subn0', type is output 
subn0    = !_LC2_B16;

-- Node name is 'subn1' 
-- Equation name is 'subn1', type is output 
subn1    =  _LC1_B16;

-- Node name is 'subn2' 
-- Equation name is 'subn2', type is output 
subn2    =  _LC5_B16;

-- Node name is 'subn3' 
-- Equation name is 'subn3', type is output 
subn3    =  _LC5_C23;

-- Node name is 'subn4' 
-- Equation name is 'subn4', type is output 
subn4    =  _LC1_C23;

-- Node name is 'subn5' 
-- Equation name is 'subn5', type is output 
subn5    =  _LC4_C23;

-- Node name is 'subn6' 
-- Equation name is 'subn6', type is output 
subn6    =  _LC7_C23;

-- Node name is 'subn7' 
-- Equation name is 'subn7', type is output 
subn7    = !_LC6_C23;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_B16', type is buried 
_LC4_B16 = LCELL( _EQ001);
  _EQ001 =  suba1 & !subb1
         #  suba0 &  suba1
         #  suba0 & !subb1
         #  suba1 & !subb0
         # !subb0 & !subb1;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = LCELL( _EQ002);
  _EQ002 =  _LC4_B16 &  suba2
         #  _LC4_B16 & !subb2
         #  suba2 & !subb2;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC2_C23', type is buried 
_LC2_C23 = LCELL( _EQ003);
  _EQ003 =  _LC3_B16 &  suba3
         #  _LC3_B16 & !subb3
         #  suba3 & !subb3;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_C23', type is buried 
_LC3_C23 = LCELL( _EQ004);
  _EQ004 =  _LC2_C23 &  suba4
         #  _LC2_C23 & !subb4
         #  suba4 & !subb4;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|pcarry5' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_C23', type is buried 
_LC8_C23 = LCELL( _EQ005);
  _EQ005 =  _LC3_C23 & !subb5
         #  _LC3_C23 &  suba5
         #  suba5 & !subb5;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|:147' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC2_B16', type is buried 
_LC2_B16 = LCELL( _EQ006);
  _EQ006 =  suba0 &  subb0
         # !suba0 & !subb0;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|:155' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC6_C23', type is buried 
_LC6_C23 = LCELL( _EQ007);
  _EQ007 =  _LC8_C23 & !suba7 & !subb6
         #  _LC8_C23 &  suba6 & !suba7
         #  suba6 & !suba7 & !subb6
         # !suba6 &  suba7 &  subb6
         # !_LC8_C23 &  suba7 &  subb6
         # !_LC8_C23 & !suba6 &  suba7;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|:156' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_B16', type is buried 
_LC1_B16 = LCELL( _EQ008);
  _EQ008 =  suba0 &  suba1 & !subb1
         #  suba1 & !subb0 & !subb1
         # !suba0 &  suba1 &  subb0 &  subb1
         # !suba0 & !suba1 &  subb0 & !subb1
         #  suba0 & !suba1 &  subb1
         # !suba1 & !subb0 &  subb1;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|:157' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_B16', type is buried 
_LC5_B16 = LCELL( _EQ009);
  _EQ009 =  _LC4_B16 &  suba2 & !subb2
         # !_LC4_B16 &  suba2 &  subb2
         # !_LC4_B16 & !suba2 & !subb2
         #  _LC4_B16 & !suba2 &  subb2;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|:158' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_C23', type is buried 
_LC5_C23 = LCELL( _EQ010);
  _EQ010 =  _LC3_B16 &  suba3 & !subb3
         #  _LC3_B16 & !suba3 &  subb3
         # !_LC3_B16 &  suba3 &  subb3
         # !_LC3_B16 & !suba3 & !subb3;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|:159' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_C23', type is buried 
_LC1_C23 = LCELL( _EQ011);
  _EQ011 =  _LC2_C23 &  suba4 & !subb4
         #  _LC2_C23 & !suba4 &  subb4
         # !_LC2_C23 &  suba4 &  subb4
         # !_LC2_C23 & !suba4 & !subb4;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|:160' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC4_C23', type is buried 
_LC4_C23 = LCELL( _EQ012);
  _EQ012 =  _LC3_C23 &  suba5 & !subb5
         #  _LC3_C23 & !suba5 &  subb5
         # !_LC3_C23 & !suba5 & !subb5
         # !_LC3_C23 &  suba5 &  subb5;

-- Node name is '|LPM_ADD_SUB:24|addcore:adder|:161' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC7_C23', type is buried 
_LC7_C23 = LCELL( _EQ013);
  _EQ013 =  _LC8_C23 &  suba6 & !subb6
         #  _LC8_C23 & !suba6 &  subb6
         # !_LC8_C23 & !suba6 & !subb6
         # !_LC8_C23 &  suba6 &  subb6;



Project Information                                     e:\edashi\am\sub8b.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,696K

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