📄 reg26b.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\sin\reg26b.rpt
reg26b
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
99 - - A -- OUTPUT 0 1 0 0 DOUT0
100 - - A -- OUTPUT 0 1 0 0 DOUT1
26 - - C -- OUTPUT 0 1 0 0 DOUT2
17 - - B -- OUTPUT 0 1 0 0 DOUT3
14 - - A -- OUTPUT 0 1 0 0 DOUT4
10 - - A -- OUTPUT 0 1 0 0 DOUT5
78 - - C -- OUTPUT 0 1 0 0 DOUT6
7 - - A -- OUTPUT 0 1 0 0 DOUT7
101 - - A -- OUTPUT 0 1 0 0 DOUT8
91 - - B -- OUTPUT 0 1 0 0 DOUT9
82 - - C -- OUTPUT 0 1 0 0 DOUT10
102 - - A -- OUTPUT 0 1 0 0 DOUT11
9 - - A -- OUTPUT 0 1 0 0 DOUT12
13 - - A -- OUTPUT 0 1 0 0 DOUT13
98 - - A -- OUTPUT 0 1 0 0 DOUT14
81 - - C -- OUTPUT 0 1 0 0 DOUT15
79 - - C -- OUTPUT 0 1 0 0 DOUT16
88 - - B -- OUTPUT 0 1 0 0 DOUT17
86 - - B -- OUTPUT 0 1 0 0 DOUT18
92 - - B -- OUTPUT 0 1 0 0 DOUT19
18 - - B -- OUTPUT 0 1 0 0 DOUT20
90 - - B -- OUTPUT 0 1 0 0 DOUT21
29 - - C -- OUTPUT 0 1 0 0 DOUT22
12 - - A -- OUTPUT 0 1 0 0 DOUT23
60 - - - 12 OUTPUT 0 1 0 0 DOUT24
87 - - B -- OUTPUT 0 1 0 0 DOUT25
31 - - C -- OUTPUT 0 1 0 0 DOUT26
116 - - - 05 OUTPUT 0 1 0 0 DOUT27
20 - - B -- OUTPUT 0 1 0 0 DOUT28
32 - - C -- OUTPUT 0 1 0 0 DOUT29
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\sin\reg26b.rpt
reg26b
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - C 19 DFFE + 1 0 1 0 :32
- 4 - B 15 DFFE + 1 0 1 0 :34
- 4 - A 06 DFFE + 1 0 1 0 :36
- 6 - C 17 DFFE + 1 0 1 0 :38
- 7 - B 07 DFFE + 1 0 1 0 :40
- 4 - C 11 DFFE + 1 0 1 0 :42
- 5 - A 14 DFFE + 1 0 1 0 :44
- 4 - C 20 DFFE + 1 0 1 0 :46
- 4 - B 01 DFFE + 1 0 1 0 :48
- 1 - B 20 DFFE + 1 0 1 0 :50
- 1 - B 12 DFFE + 1 0 1 0 :52
- 8 - B 08 DFFE + 1 0 1 0 :54
- 6 - B 09 DFFE + 1 0 1 0 :56
- 5 - C 12 DFFE + 1 0 1 0 :58
- 3 - C 09 DFFE + 1 0 1 0 :60
- 5 - A 07 DFFE + 1 0 1 0 :62
- 7 - A 16 DFFE + 1 0 1 0 :64
- 2 - A 18 DFFE + 1 0 1 0 :66
- 1 - A 11 DFFE + 1 0 1 0 :68
- 2 - C 12 DFFE + 1 0 1 0 :70
- 2 - B 07 DFFE + 1 0 1 0 :72
- 2 - A 03 DFFE + 1 0 1 0 :74
- 1 - A 23 DFFE + 1 0 1 0 :76
- 7 - C 05 DFFE + 1 0 1 0 :78
- 4 - A 15 DFFE + 1 0 1 0 :80
- 8 - A 21 DFFE + 1 0 1 0 :82
- 1 - B 14 DFFE + 1 0 1 0 :84
- 1 - C 18 DFFE + 1 0 1 0 :86
- 2 - A 06 DFFE + 1 0 1 0 :88
- 4 - A 09 DFFE + 1 0 1 0 :90
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\sin\reg26b.rpt
reg26b
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 6/ 48( 12%) 7/ 48( 14%) 5/16( 31%) 11/16( 68%) 0/16( 0%)
B: 8/ 96( 8%) 5/ 48( 10%) 4/ 48( 8%) 5/16( 31%) 9/16( 56%) 0/16( 0%)
C: 9/ 96( 9%) 3/ 48( 6%) 4/ 48( 8%) 6/16( 37%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\sin\reg26b.rpt
reg26b
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 30 CLK
Device-Specific Information: f:\sin\reg26b.rpt
reg26b
** EQUATIONS **
CLK : INPUT;
DIN0 : INPUT;
DIN1 : INPUT;
DIN2 : INPUT;
DIN3 : INPUT;
DIN4 : INPUT;
DIN5 : INPUT;
DIN6 : INPUT;
DIN7 : INPUT;
DIN8 : INPUT;
DIN9 : INPUT;
DIN10 : INPUT;
DIN11 : INPUT;
DIN12 : INPUT;
DIN13 : INPUT;
DIN14 : INPUT;
DIN15 : INPUT;
DIN16 : INPUT;
DIN17 : INPUT;
DIN18 : INPUT;
DIN19 : INPUT;
DIN20 : INPUT;
DIN21 : INPUT;
DIN22 : INPUT;
DIN23 : INPUT;
DIN24 : INPUT;
DIN25 : INPUT;
DIN26 : INPUT;
DIN27 : INPUT;
DIN28 : INPUT;
DIN29 : INPUT;
-- Node name is 'DOUT0'
-- Equation name is 'DOUT0', type is output
DOUT0 = _LC4_A9;
-- Node name is 'DOUT1'
-- Equation name is 'DOUT1', type is output
DOUT1 = _LC2_A6;
-- Node name is 'DOUT2'
-- Equation name is 'DOUT2', type is output
DOUT2 = _LC1_C18;
-- Node name is 'DOUT3'
-- Equation name is 'DOUT3', type is output
DOUT3 = _LC1_B14;
-- Node name is 'DOUT4'
-- Equation name is 'DOUT4', type is output
DOUT4 = _LC8_A21;
-- Node name is 'DOUT5'
-- Equation name is 'DOUT5', type is output
DOUT5 = _LC4_A15;
-- Node name is 'DOUT6'
-- Equation name is 'DOUT6', type is output
DOUT6 = _LC7_C5;
-- Node name is 'DOUT7'
-- Equation name is 'DOUT7', type is output
DOUT7 = _LC1_A23;
-- Node name is 'DOUT8'
-- Equation name is 'DOUT8', type is output
DOUT8 = _LC2_A3;
-- Node name is 'DOUT9'
-- Equation name is 'DOUT9', type is output
DOUT9 = _LC2_B7;
-- Node name is 'DOUT10'
-- Equation name is 'DOUT10', type is output
DOUT10 = _LC2_C12;
-- Node name is 'DOUT11'
-- Equation name is 'DOUT11', type is output
DOUT11 = _LC1_A11;
-- Node name is 'DOUT12'
-- Equation name is 'DOUT12', type is output
DOUT12 = _LC2_A18;
-- Node name is 'DOUT13'
-- Equation name is 'DOUT13', type is output
DOUT13 = _LC7_A16;
-- Node name is 'DOUT14'
-- Equation name is 'DOUT14', type is output
DOUT14 = _LC5_A7;
-- Node name is 'DOUT15'
-- Equation name is 'DOUT15', type is output
DOUT15 = _LC3_C9;
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