adder26b.vhd

来自「dds信号发生器」· VHDL 代码 · 共 13 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ADDER26B is
  port(A26B:in std_logic_vector(29 downto 0);
       B26B:in std_logic_vector(29 downto 0);
       S26B:out std_logic_vector(29 downto 0));
end;
architecture ONE of ADDER26B is
begin
S26B<=A26B+B26B;
end;