addq1.vhd

来自「dds信号发生器」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addq1 is
port(ma:in std_logic_vector(3 downto 0);
     maout:out std_logic_vector(7 downto 0));
end;
architecture one of addq1 is
begin
process(ma)
begin
case ma is
   when "0000"=>maout<="11111111";
   when "0001"=>maout<="11100101";
   when "0010"=>maout<="11001100";
   when "0011"=>maout<="10110010";
   when "0100"=>maout<="10011001";
   when "0101"=>maout<="01111111";
   when "0110"=>maout<="01100110";
   when "0111"=>maout<="01001100";
   when "1000"=>maout<="00110011";
   when "1001"=>maout<="00011001";
   when others=>maout<="00000000";
end case;
end process;
end;