div22.vhd

来自「dds信号发生器」· VHDL 代码 · 共 20 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div22 is
port(q2:in std_logic_vector(7 downto 0);
     q2out:out std_logic_vector(6 downto 0));
end;
architecture one of div22 is
begin
q2out(6)<=q2(7);
q2out(5)<=q2(6);
q2out(4)<=q2(5);
q2out(3)<=q2(4);
q2out(2)<=q2(3);
q2out(1)<=q2(2);
q2out(0)<=q2(1);
end;