fshow.srr

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$ Start of Compile
#Tue May 02 18:43:30 2006

Synplify VHDL Compiler, version 5.1.2, built Apr 14 1999
Copyright (C) 1994-1999, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!
Synthesizing work.fshow.one
@W:"f:\sin\fshow.vhd":49:0:49:6|Incomplete sensitivity list - assuming completeness
@W:"f:\sin\fshow.vhd":53:18:53:19|Referenced variable m5 is not in sensitivity list
Post processing for work.fshow.one
@END
Process took 0.11 seconds realtime, 0.11 seconds cputime
Synplify Actel Technology Mapper, version 5.1.2, built Apr 14 1999
Copyright (C) 1994-1999, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 16
Automatic dissolve during optimization of view:work.fshow(one) of fadd5t_9t5(fadd5t)
Automatic dissolve during optimization of view:work.fshow(one) of fadd5_4t0(fadd5)
Automatic dissolve during optimization of view:work.fshow(one) of I_90(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_89(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_88(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_87(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_86(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_85(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_84(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_83(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_82(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_81(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_80(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_79(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_78(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_77(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_76(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_75(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_74(ha)
Automatic dissolve during optimization of view:work.fshow(one) of I_73(fabase1)
Automatic dissolve during optimization of view:work.fshow(one) of I_72(ha)
Automatic dissolve during optimization of view:work.fshow(one) of I_67(inc4)
Automatic dissolve during optimization of view:work.fshow(one) of I_62(inc4)
Automatic dissolve during optimization of view:work.fshow(one) of I_57(inc4)
Automatic dissolve during optimization of view:work.fshow(one) of I_52(inc4)
Automatic dissolve during optimization of view:work.fshow(one) of fadd4_nc_3t0(fadd4_nc)
Automatic dissolve during optimization of view:work.fshow(one) of fadd2_nc_1t0(fadd2_nc)
Automatic dissolve during optimization of view:work.fshow(one) of fadd3_nc_2t0(fadd3_nc)
Automatic dissolve during optimization of view:work.fshow(one) of fadd1_6t6(fadd1)
Automatic dissolve during optimization of view:work.fshow(one) of fadd6_nc_5t0(fadd6_nc)
Automatic dissolve during optimization of view:work.fshow(one) of fadd1_6t6(fadd1)
Automatic dissolve during optimization of view:work.fshow(one) of fadd6_nc_5t0(fadd6_nc)
Automatic dissolve during optimization of view:work.fshow(one) of fadd3_nc_2t0(fadd3_nc)
Automatic dissolve during optimization of view:work.fshow(one) of I_11(inc3)
Automatic dissolve during optimization of view:work.fshow(one) of fadd5_nc_4t0(fadd5_nc)

Added 0 Buffers
Added 0 Cells via replication
Synthesized design as a chip
---------------------------------------
Resource Usage Report 

Target Part: a3265dx-s
Combinational Cells: 195
Sequential Cells:    56 of 510 (11%)
Total Cells:         251 of 985 (26%)
Clock Buffers:       2
IO Cells:            30

Details:
   and2:           7	comb:1
   and3:           1	comb:1
   ax1c:           4	comb:1
   cm8:            62	comb:1
   cy2a:           16	comb:1
   cy2b:           1	comb:1
   maj3:           22	comb:1
   or2:            2	comb:1
   or2b:           2	comb:1
   or4:            4	comb:1
   xa1:            2	comb:1
   xnor2:          15	comb:1
   xor2:           57	comb:1

   df1:            17	seq:1
   dfm7a:          39	seq:1

   clkbuf:         2	clock buffer
   inbuf:          2	
   outbuf:         26	


		 ##### START TIMING REPORT #####
Set the Environment Variable SYNPLIFY_TIMING_REPORT_OLD to get the old timing report 


		 Performance Summary 
		*********************

          Requested     Estimated     Requested     Estimated          
Clock     Frequency     Frequency     Period        Period        Slack
-----------------------------------------------------------------------
clk2      1.0 MHz       18.5 MHz      1000.0        54.0          946.0
clk3      1.0 MHz       18.3 MHz      1000.0        54.6          945.4
clk1      1.0 MHz       17.1 MHz      1000.0        58.6          941.4
clk0      1.0 MHz       18.3 MHz      1000.0        54.6          945.4
=======================================================================


		 Interface Information 
		***********************

Input Ports: 

Port     Reference     User           Arrival     Required          
Name     Clock         Constraint     Time        Time         Slack
--------------------------------------------------------------------
====================================================================


Output Ports: 

Port      Reference     User           Arrival     Required          
Name      Clock         Constraint     Time        Time         Slack
---------------------------------------------------------------------
f[0]      clk2          0.0            31.8        1000.0       968.2
f[1]      clk2          0.0            31.8        1000.0       968.2
f[2]      clk2          0.0            31.8        1000.0       968.2
f[3]      clk2          0.0            31.8        1000.0       968.2
f[4]      clk2          0.0            42.2        1000.0       957.8
f[5]      clk2          0.0            31.8        1000.0       968.2
f[6]      clk2          0.0            31.8        1000.0       968.2
f[7]      clk2          0.0            31.8        1000.0       968.2
f[8]      clk2          0.0            31.8        1000.0       968.2
f[9]      clk2          0.0            31.8        1000.0       968.2
f[10]     clk2          0.0            31.8        1000.0       968.2
f[11]     clk2          0.0            31.8        1000.0       968.2
f[12]     clk2          0.0            26.9        1000.0       973.1
m4[0]     clk0          0.0            42.2        1000.0       957.8
m4[1]     clk0          0.0            42.9        1000.0       957.1
m4[2]     clk0          0.0            42.5        1000.0       957.5
m4[3]     clk0          0.0            52.3        1000.0       947.7
m4[4]     clk0          0.0            47.5        1000.0       952.5
m4[5]     clk0          0.0            54.6        1000.0       945.4
m4[6]     clk0          0.0            49.7        1000.0       950.3
m4[7]     clk0          0.0            54.6        1000.0       945.4
m4[8]     clk0          0.0            53.6        1000.0       946.4
m4[9]     clk0          0.0            53.6        1000.0       946.4
=====================================================================


		Detailed Timing Report for  clock : clk2 
		*******************************************
Requested Period 	  1000.0 ns
Estimated Period 	  54.0 ns
Worst Slack 	 	 946.0 ns

Start Points for Paths with Slack Worse than 950.9 ns : 

                                        Arrival          
Instance     Type     Pin     Net       Time        Slack
---------------------------------------------------------
m2[1]        df1      q       m2[1]     7.1         950.6
=========================================================


No End Points with Slack Worse than 950.9 ns Found


 Cannot Find any complete critical path