📄 am.rpt
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F4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 14/22( 63%)
F5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F6 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
F7 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/22( 45%)
F8 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 8/22( 36%)
F9 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 13/22( 59%)
F10 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 4/22( 18%)
F11 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
F14 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 13/22( 59%)
F15 1/ 8( 12%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 3/22( 13%)
F16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
F17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 6/22( 27%)
F19 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 7/22( 31%)
F21 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 0/2 0/2 11/22( 50%)
F23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
F24 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 12/22( 54%)
F26 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
F27 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
F30 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 9/22( 40%)
F31 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/22( 45%)
F32 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
F33 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
F34 7/ 8( 87%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F35 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
F36 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 23/96 ( 23%)
Total logic cells used: 292/1728 ( 16%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.44/4 ( 86%)
Total fan-in: 1006/6912 ( 14%)
Total input pins required: 17
Total input I/O cell registers required: 0
Total output pins required: 12
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 292
Total flipflops required: 4
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 53/1728 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 8 8 0 8 8 8 3 8 0 0 0 8 8 8 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 91/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 8 0 0 8 8 8 8 8 8 8 8 0 1 8 1 8 8 0 0 8 0 8 0 8 8 0 8 8 0 0 8 8 8 8 7 8 8 201/0
Total: 16 8 0 16 16 16 11 16 8 8 8 8 9 16 1 16 16 0 0 8 0 8 0 8 8 0 8 8 0 0 8 8 8 8 7 8 8 292/0
Device-Specific Information: e:\edashi\am\am.rpt
am
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G ^ 0 0 0 0 clk5
122 - - - 18 INPUT ^ 0 0 0 7 fout0
65 - - - 09 INPUT ^ 0 0 0 9 fout1
14 - - C -- INPUT ^ 0 0 0 10 fout2
17 - - C -- INPUT ^ 0 0 0 10 fout3
95 - - C -- INPUT ^ 0 0 0 10 fout4
11 - - C -- INPUT ^ 0 0 0 10 fout5
12 - - C -- INPUT ^ 0 0 0 11 fout6
97 - - C -- INPUT ^ 0 0 0 9 fout7
79 - - F -- INPUT ^ 0 0 0 10 fz0
132 - - - 26 INPUT ^ 0 0 0 9 fz1
54 - - - -- INPUT ^ 0 0 0 15 fz2
56 - - - -- INPUT ^ 0 0 0 14 fz3
126 - - - -- INPUT ^ 0 0 0 15 fz4
125 - - - -- INPUT ^ 0 0 0 14 fz5
32 - - F -- INPUT ^ 0 0 0 13 fz6
124 - - - -- INPUT ^ 0 0 0 12 fz7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\edashi\am\am.rpt
am
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
31 - - F -- OUTPUT 0 1 0 0 amout0
30 - - F -- OUTPUT 0 1 0 0 amout1
33 - - F -- OUTPUT 0 1 0 0 amout2
78 - - F -- OUTPUT 0 1 0 0 amout3
81 - - F -- OUTPUT 0 1 0 0 amout4
69 - - - 06 OUTPUT 0 1 0 0 amout5
80 - - F -- OUTPUT 0 1 0 0 amout6
82 - - F -- OUTPUT 0 1 0 0 amout7
70 - - - 05 OUTPUT 0 1 0 0 maout0
114 - - - 06 OUTPUT 0 1 0 0 maout1
113 - - - 05 OUTPUT 0 1 0 0 maout2
96 - - C -- OUTPUT 0 1 0 0 maout3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
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