📄 am.rpt
字号:
|mashuchu:8|lpm_add_sub:52|addcore:adder|
|mashuchu:8|lpm_add_sub:52|altshift:result_ext_latency_ffs|
|mashuchu:8|lpm_add_sub:52|altshift:carry_ext_latency_ffs|
|mashuchu:8|lpm_add_sub:52|altshift:oflow_ext_latency_ffs|
|div2:12|
|div256:13|
|sub8b:14|
|sub8b:14|lpm_add_sub:24|
|sub8b:14|lpm_add_sub:24|addcore:adder|
|sub8b:14|lpm_add_sub:24|altshift:result_ext_latency_ffs|
|sub8b:14|lpm_add_sub:24|altshift:carry_ext_latency_ffs|
|sub8b:14|lpm_add_sub:24|altshift:oflow_ext_latency_ffs|
|div22:15|
|add128:16|
|add128:16|lpm_add_sub:17|
|add128:16|lpm_add_sub:17|addcore:adder|
|add128:16|lpm_add_sub:17|altshift:result_ext_latency_ffs|
|add128:16|lpm_add_sub:17|altshift:carry_ext_latency_ffs|
|add128:16|lpm_add_sub:17|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\edashi\am\am.rpt
am
***** Logic for device 'am' compiled without errors.
Device: EP1K30TC144-3
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E E E E E E E
S S S S S S S S S S S S S V S S S S S S m m S S S S
E E E E E E E E E V E E E E C f E E E E E E V a a E E E E
R R R R R R R R R C R R R R C o R R R R R R C o o R R R R
V V V V V G V V V V C V f V V G V I f f f G u V V V V V V C u u V V V V
E E E E E N E E E E I E z E E N E N z z z N t E E E E E E I t t E E E E
D D D D D D D D D D O D 1 D D D D T 4 5 7 D 0 D D D D D D O 1 2 D D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GND
GND | 6 103 | VCCINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | RESERVED
RESERVED | 9 100 | RESERVED
RESERVED | 10 99 | RESERVED
fout5 | 11 98 | RESERVED
fout6 | 12 97 | fout7
RESERVED | 13 96 | maout3
fout2 | 14 95 | fout4
GND | 15 94 | VCCIO
VCCINT | 16 93 | GND
fout3 | 17 92 | RESERVED
RESERVED | 18 91 | RESERVED
RESERVED | 19 EP1K30TC144-3 90 | RESERVED
RESERVED | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | RESERVED
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | VCCINT
GND | 25 84 | GND
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | amout7
RESERVED | 28 81 | amout4
RESERVED | 29 80 | amout6
amout1 | 30 79 | fz0
amout0 | 31 78 | amout3
fz6 | 32 77 | ^MSEL0
amout2 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R R R R V R R R R V R G V f c f G G R R V R R R f G R R a m V R
E E E N E E E E C E E E E C E N C z l z N N E E C E E E o N E E m a C E
S S S D S S S S C S S S S C S D C 2 k 3 D D S S C S S S u D S S o o C S
E E E E E E E I E E E E I E I 5 E E I E E E t E E u u I E
R R R R R R R O R R R R N R N R R O R R R 1 R R t t O R
V V V V V V V V V V V T V T V V V V V V V 5 0 V
E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\edashi\am\am.rpt
am
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
C1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/22( 31%)
C2 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
C4 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/22( 50%)
C5 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 1/2 0/2 5/22( 22%)
C6 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 7/22( 31%)
C7 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 6/22( 27%)
C8 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 6/22( 27%)
C12 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 5/22( 22%)
C13 8/ 8(100%) 4/ 8( 50%) 0/ 8( 0%) 0/2 0/2 7/22( 31%)
C14 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
C16 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
C17 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
F1 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/22( 40%)
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