hello.v

来自「一个带波形输出的扫频模板systemC源程序」· Verilog 代码 · 共 44 行

module hello (input clk,reset
,output reg q
);

reg[3:0]  temp1,temp2;

always @(posedge clk,posedge reset)
begin 
    hello1;
end



task hello1;
begin 
    if(reset)
	   begin 
	       temp1=0;
	       temp2=0;
	   end
	   else 
	   if(temp1>=temp2)
	   begin  
	       
	       if(temp2>=0)
	       begin 
	           temp2=temp2-1;
	       end
	       else
	       begin 
	           temp2=15;
	       end
	       temp1=0;
	       q=~q;
	         	     
	   end
	   else
	   begin 
	       temp1=temp1+1;
	   end
end
endtask

endmodule