cla_tb.vhd

来自「超前进位加法器的例子,包括源码和测试文件,压缩包,无密码.」· VHDL 代码 · 共 61 行

LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL;
    USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY cla_tb IS
END cla_tb;

ARCHITECTURE RTL OF cla_tb IS

    COMPONENT cla
        PORT
        (
        a           : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);
        b           : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);
        c           : OUT   STD_LOGIC;
        s           : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0)
        );
    END COMPONENT;

    SIGNAL  s       : STD_LOGIC_VECTOR(8 DOWNTO 0);

    SIGNAL clk      : STD_LOGIC := '0';
    SIGNAL count1   : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
    SIGNAL count2   : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');


BEGIN

        inst_cla : cla
        PORT MAP
            (
            a           => count1      ,
            b           => count2      ,
            c           => s(8)        ,
            s           => s( 7 DOWNTO 0)
            );

    clk     <= NOT clk AFTER 5 ns;

    count1_logic : PROCESS(clk)
    BEGIN
        IF(clk'EVENT AND clk = '1')THEN
            count1  <= count1 + 1;
        END IF;
    END PROCESS;

    count2_logic : PROCESS(clk)
    BEGIN
        IF(clk'EVENT AND clk = '1')THEN
            IF(count1 = "11111111")THEN
                count2  <= count2 + 1;
            END IF;
        END IF;
    END PROCESS;





END RTL;