control.v

来自「串口通信程序.在波特率为9600的串口通信程序」· Verilog 代码 · 共 69 行

module cntrol(
    reset,rst,clk16x,tsre,tbre,din,dout,rdn,wrn,led,data_ready
);

    input reset;
    input clk16x;
    input tsre;
    input tbre;
    input data_ready;
    output rst;
    output [7:0] din;
    input  [7:0] dout;
    output [7:0] led;
    output       wrn;
    output       rdn;
    
    reg    [7:0] counter;
    reg    [7:0] delay;
    reg    [7:0] din;
    reg    [7:0] data_temp;
    reg          wrn;
    reg          rdn;


assign rst = !reset;

always @(posedge tsre)
if(rst)
   counter[7:0] = 8'h0;
else
   counter[7:0] = counter[7:0] + 1;

assign led[7:0] = counter[7:0];

always @(posedge clk16x or posedge rst)
if(rst)
    delay[7:0] = 0;
else if(data_ready == 1)
   delay[7:0] = 0;
else 
   delay[7:0] = delay[7:0] + 1;

always @(posedge clk16x)
    if(2 <= delay[7:0] && delay[7:0] <= 5)
        rdn = 0;
    else
        rdn = 1;
            
always @(posedge clk16x)
    if(3 <= delay[7:0] && delay[7:0] <= 4)
        data_temp = dout;
    else
        data_temp = data_temp;

always @(posedge clk16x)
    if(9 <= delay[7:0] && delay[7:0] <= 12)
        wrn = 0;
    else
        wrn = 1;
            
always @(posedge clk16x)
    if(7 <= delay[7:0] && delay[7:0] <= 13)
        din = data_temp;
    else
        din = data_temp;
        


endmodule