baud_clk.v

来自「串口通信程序.在波特率为9600的串口通信程序」· Verilog 代码 · 共 27 行

module baud_clk(rst,clk32m,clk16x);
    input rst;
    input clk32m;
    output clk16x;

    reg clk16x;
    reg [7:0] baud_con; 

    always @(posedge clk32m)
    if(rst)
        baud_con = 0;
    else if(0 <= baud_con && baud_con <= 208)
        baud_con = baud_con + 1;
    else
        baud_con = 0;

    always @(posedge clk32m)
    if(rst)
        clk16x = 0;
    else if(0 <= baud_con && baud_con <= 104)
        clk16x = 0;
    else
        clk16x = 1;
           

endmodule