uart_tf.v

来自「串口通信程序.在波特率为9600的串口通信程序」· Verilog 代码 · 共 33 行

`timescale 1ns/1ns
module uart_tf();

wire tbre ;
wire tsre ;
wire sdo ;
reg [7:0] din ;
reg reset ;
reg clk32m ;
reg wrn ;
reg rxd ;
reg rdn ;
wire [7:0] dout ;
wire data_ready ;
wire framing_error ;
wire parity_error ;


initial begin
reset = 1;
#100 reset = 0;
#100 reset = 1;
end

initial begin
clk32m = 0;
end

always #16 clk32m = !clk32m;
 uart UT(dout,data_ready,framing_error,parity_error,rxd,clk32m,reset,rdn,tbre,tsre,sdo);

endmodule