📄 scu_all_fpga.v
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//IC12,4 PCM DSP,6PCM POTS; 16 UART,16 INTn,16 RSTn,2M CLK4;DPLL,60x Bus,BITS; 12 PCM POTS,4 PCM DSP.
// +-------------+
// DPLL<------>| |<------->2M CLK4
// 60x Bus<------>| |<------->16 UART
// BITS<------>| FPGA |<------->16 INTn
// 4 PCM DSP<------>| |<------->16 RSTn
// 6 PCM POTS<------>| |<------->12 PCM POTS
// | |<------->4 PCM DSP
// +-------------+
module scu_all_fpga(l60x_clkout,M_DATA,M_ADDR,M_OEn,M_WEn,M_IRQ5n,M_CS7n,PORESETn,HRESETn,
presentBn,pauseVaildBn,reqBn,msinn,msoutAn,msoutBn,pauseAnOut,reqAnOut,
DPLL_NORMAL,DPLL_HOLDOVER,DPLL_FREERUN,DPLL_LOCK,DPLL_MONITOR1,DPLL_MONITOR2,
DPLL_TCLR,DPLL_MUXSEL,DPLL_FLOCK,DPLL_RESET,DPLL_MODEL1,DPLL_MODEL0,TSI_ODE,
BITS_THZ,TSI_RESETn,BITS_RESET,MR_IN,FP_LED1,FP_LED2,MS_ADDRESS,
SW_EDO,SW_EDI,SW_ESK,SW_ECS,SW_RESETn,test_tick);
output test_tick;
input l60x_clkout;
inout [7:0] M_DATA;
input [31:22] M_ADDR;
input M_OEn;
input M_WEn;
output M_IRQ5n;
input M_CS7n;
input PORESETn;
inout HRESETn;
input presentBn;
input pauseVaildBn;
input reqBn;
input msinn; /*MS state from other arbiter pull down */
output msoutAn;
output msoutBn;
output pauseAnOut;
output reqAnOut;
input SW_EDO;
output SW_EDI;
output SW_ESK;
output SW_ECS;
output SW_RESETn;
input DPLL_NORMAL;
input DPLL_HOLDOVER;
input DPLL_FREERUN;
input DPLL_LOCK;
input DPLL_MONITOR1;
input DPLL_MONITOR2;
input MR_IN;
input MS_ADDRESS;
output DPLL_TCLR;
output DPLL_MUXSEL;
output DPLL_FLOCK;
output DPLL_RESET;
output DPLL_MODEL1;
output DPLL_MODEL0;
output TSI_ODE;
output BITS_THZ;
output TSI_RESETn;
output BITS_RESET;
output FP_LED1;
output FP_LED2;
wire pauseAn;
wire reqAn;
wire GLOBE_RESETn;
reg manswitch;
reg manreset;
reg [0:7] countMR;
reg [0:7] count1Reg;
reg pauseAn_record;
reg pauseVaildAn;
wire pauseVaildAn_manreset;
wire [0:5] instate;
reg [1:0] outstate;
wire [0:7] count1temp;
wire [0:7] count1;
wire [0:3] count1cs;
wire hageneralCs;
wire [0:7] hageneral;
reg tick100ms;
reg [0:21] count100ms;
wire HRESETn;
wire count1Start;
wire M_ADDR_ALL;
wire [1:0] msstate_now;
assign GLOBE_RESETn = PORESETn & HRESETn;
assign M_ADDR_ALL = (M_ADDR[22]) | (!M_ADDR[23])| M_ADDR[24] | M_ADDR[25] | M_ADDR[26];
assign count1cs[0] = M_CS7n | M_ADDR_ALL | (M_ADDR[27])
| (M_ADDR[28]) | (M_ADDR[29]) | (M_ADDR[30]) | (M_ADDR[31]);
myreg countreg0(
.data(M_DATA),
.csn(count1cs[0]),
.wen(M_WEn),
.oen(M_OEn),
.rgValue(count1temp[0:7]),
.rstn(GLOBE_RESETn)
);
assign count1[0] = count1temp[7];
assign count1[1] = count1temp[6];
assign count1[2] = count1temp[5];
assign count1[3] = count1temp[4];
assign count1[4] = count1temp[3];
assign count1[5] = count1temp[2];
assign count1[6] = count1temp[1];
assign count1[7] = count1temp[0];
assign hageneralCs = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (M_ADDR[28]) | (M_ADDR[29]) | (M_ADDR[30]) | (!M_ADDR[31]);
myreg hageneralReg(
.data(M_DATA),
.csn(hageneralCs),
.wen(M_WEn),
.oen(M_OEn),
.rgValue(hageneral),
.rstn(GLOBE_RESETn)
);
assign pauseAn = hageneral[2];
assign reqAn = ~hageneral[3];
assign count1Start = hageneral[0];
/*100mS base timing*/
always @(posedge l60x_clkout)
begin
if(count100ms == 22'b000000000000000000000)
begin
tick100ms = 1'b1;
count100ms = 22'b1111111111111111111111;
end
else
begin
if(count100ms == 22'b1000000000000000000000)
tick100ms = 1'b0;
count100ms = count100ms - 1;
end
end
/*for test */
assign test_tick = tick100ms;
always@(posedge tick100ms or negedge GLOBE_RESETn )
begin
if(!GLOBE_RESETn)
begin
countMR = 1'b0;
manswitch = 1'b1;
manreset = 1'b1;
end
else
begin
if(!MR_IN)
countMR = countMR + 1;
else
countMR = 1'b0;
if(countMR >= 80)
begin
manswitch = 1'b0;
manreset = 1'b0;
end
else if(countMR >= 10)
begin
manswitch = 1'b0;
manreset = 1'b1;
end
else
begin
manswitch = 1'b1;
manreset = 1'b1;
end
end
end
reg HRESETn1;
always@(posedge tick100ms)
begin
HRESETn1 = manreset;
end
assign HRESETn = (HRESETn1)?1'bz:1'b0;
wire clr;
assign clr = pauseAn_record ^ pauseAn;
always@(posedge tick100ms or negedge GLOBE_RESETn or posedge clr)
begin
if(!GLOBE_RESETn)
begin
count1Reg = count1;
pauseVaildAn = 1'b1;
pauseAn_record = 1'b1;
end
else if(clr)
begin
count1Reg = count1;
pauseVaildAn = 1'b0;
pauseAn_record = pauseAn;
end
else if(count1Start)
begin
if(count1Reg == 8'h00)
begin
count1Reg = count1;
pauseVaildAn = 1'b1;
end
else
begin
count1Reg = count1Reg - 1;
end
end
end
assign pauseVaildAn_manreset = pauseVaildAn | (~manswitch);
assign instate[0:5] = {presentBn,pauseVaildAn_manreset,pauseVaildBn,reqAn,reqBn,msinn};
always@(instate)
begin
casez(instate)
/*6'b1????? : outstate = 2'b01; */
6'b11???? : outstate = 2'b11;
6'b10???? : outstate = 2'b01;
6'b001??0 : outstate = 2'b01;
6'b001??1 : outstate = 2'b11;
6'b010??? : outstate = 2'b10;
6'b000011 : outstate = 2'b11;
6'b000010 : outstate = 2'b01;
6'b00010? : outstate = 2'b10;
endcase
end
assign msoutAn = outstate[1];
assign msoutBn = outstate[0];
assign msstate_now = outstate;
assign pauseAnOut = pauseVaildAn;
assign reqAnOut = reqAn;
assign msstateRegCs1 = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (M_ADDR[28]) | (M_ADDR[29]) | (!M_ADDR[30]) | (M_ADDR[31]);
assign msstateRegCs2 = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (M_ADDR[28]) | (M_ADDR[29]) | (!M_ADDR[30]) | (!M_ADDR[31]);
myextreg msstateReg1(
.data(M_DATA),
.csn(msstateRegCs1),
.oen(M_OEn),
.mem({1'b0,MS_ADDRESS,instate[0:5]})
);
myextreg msstateReg2(
.data(M_DATA),
.csn(msstateRegCs2),
.oen(M_OEn),
.mem({msstate_now,6'b101010})
);
/***************************************************************************************/
/*DPLL CTL */
/*
DPLL_TCLR,DPLL_MUXSEL,DPLL_FLOCK,DPLL_RESET,DPLL_MONITOR1,DPLL_MONITOR2,
DPLL_MODEL1/0,DPLL_NORMAL/HOLDOVER/FREERUN,DPLL_LOCK
*/
wire dpllctlregcs;
wire [0:7] dpllctlreg;
wire dpllclrIntRegCs;
wire [0:7] dpllclrIntData;
wire dpllIntStateRegCs;
reg [0:7] dpllintState;
wire [0:7] dpllintStateValue;
wire dpllIntMaskRegCs;
wire [0:7] dpllIntMask;
wire dpllstatechangeInt;
wire dpllstateCs;
wire [0:7] dpllstate;
assign dpllstateCs = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (M_ADDR[28]) | (!M_ADDR[29]) | (M_ADDR[30]) | (!M_ADDR[31]);
assign dpllstate = {1'b1,1'b0,DPLL_MONITOR2,DPLL_MONITOR1,DPLL_LOCK,DPLL_FREERUN,DPLL_HOLDOVER,DPLL_NORMAL};
myextreg dpllstateReg1(
.data(M_DATA),
.csn(dpllstateCs),
.oen(M_OEn),
.mem(dpllstate)
);
/* dpllintStateReg1 for dpll state change */
assign dpllIntStateRegCs = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (M_ADDR[28]) | (!M_ADDR[29]) | (!M_ADDR[30]) | (M_ADDR[31]);
assign dpllintStateValue = dpllintState;
myextreg dpllintStateReg1(
.data(M_DATA),
.csn(dpllIntStateRegCs),
.oen(M_OEn),
.mem(dpllintStateValue)
);
assign dpllIntMaskRegCs = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (M_ADDR[28]) | (!M_ADDR[29]) | (!M_ADDR[30]) | (!M_ADDR[31]);
myreg dpllIntMaskReg1(
.data(M_DATA),
.csn(dpllIntMaskRegCs),
.wen(M_WEn),
.oen(M_OEn),
.rgValue(dpllIntMask),
.rstn(GLOBE_RESETn)
);
/* int clr write 1 to clear dpllintStateReg1 */
assign dpllclrIntRegCs = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (!M_ADDR[28]) | (M_ADDR[29]) | (M_ADDR[30]) | (M_ADDR[31]);
/*
myreg dpllIntclrReg1(
.data(M_DATA),
.csn(dpllclrIntRegCs),
.wen(M_WEn),
.oen(M_OEn),
.rgValue(dpllclrIntData),
.rstn(GLOBE_RESETn)
);
*/
assign dpllclrIntData[7] = dpllclrIntRegCs | (~M_DATA[0]) | M_WEn;
assign dpllclrIntData[6] = dpllclrIntRegCs | (~M_DATA[1]) | M_WEn;
assign dpllclrIntData[5] = dpllclrIntRegCs | (~M_DATA[2]) | M_WEn;
assign dpllclrIntData[4] = dpllclrIntRegCs | (~M_DATA[3]) | M_WEn;
assign dpllclrIntData[3] = dpllclrIntRegCs | (~M_DATA[4]) | M_WEn;
assign dpllclrIntData[2] = dpllclrIntRegCs | (~M_DATA[5]) | M_WEn;
assign dpllclrIntData[1] = dpllclrIntRegCs | (~M_DATA[6]) | M_WEn;
assign dpllclrIntData[0] = dpllclrIntRegCs | (~M_DATA[7]) | M_WEn;
always@(posedge DPLL_NORMAL or negedge GLOBE_RESETn or negedge dpllclrIntData[0])
begin
if(!GLOBE_RESETn)
begin
dpllintState [0] = 1'b1;
end
else if (!dpllclrIntData[0])
begin
dpllintState [0] = 1'b1;
end
else
dpllintState [0] = 1'b0;
end
always@(negedge DPLL_NORMAL or negedge GLOBE_RESETn or negedge dpllclrIntData[1])
begin
if(!GLOBE_RESETn)
begin
dpllintState [1] = 1'b1;
end
else if (!dpllclrIntData[1])
begin
dpllintState [1] = 1'b1;
end
else
dpllintState [1] = 1'b0;
end
always@(posedge DPLL_HOLDOVER or negedge GLOBE_RESETn or negedge dpllclrIntData[2])
begin
if(!GLOBE_RESETn)
begin
dpllintState [2] = 1'b1;
end
else if (!dpllclrIntData[2])
begin
dpllintState [2] = 1'b1;
end
else
dpllintState [2] = 1'b0;
end
always@(negedge DPLL_HOLDOVER or negedge GLOBE_RESETn or negedge dpllclrIntData[3])
begin
if(!GLOBE_RESETn)
begin
dpllintState [3] = 1'b1;
end
else if (!dpllclrIntData[3])
begin
dpllintState [3] = 1'b1;
end
else
dpllintState [3] = 1'b0;
end
always@(posedge DPLL_FREERUN or negedge GLOBE_RESETn or negedge dpllclrIntData[4])
begin
if(!GLOBE_RESETn)
begin
dpllintState [4] = 1'b1;
end
else if (!dpllclrIntData[4])
begin
dpllintState [4] = 1'b1;
end
else
dpllintState [4] = 1'b0;
end
always@(negedge DPLL_FREERUN or negedge GLOBE_RESETn or negedge dpllclrIntData[5])
begin
if(!GLOBE_RESETn)
begin
dpllintState [5] = 1'b1;
end
else if (!dpllclrIntData[5])
begin
dpllintState [5] = 1'b1;
end
else
dpllintState [5] = 1'b0;
end
always@(posedge DPLL_LOCK or negedge GLOBE_RESETn or negedge dpllclrIntData[6])
begin
if(!GLOBE_RESETn)
begin
dpllintState [6] = 1'b1;
end
else if (!dpllclrIntData[6])
begin
dpllintState [6] = 1'b1;
end
else
dpllintState [6] = 1'b0;
end
always@(negedge DPLL_LOCK or negedge GLOBE_RESETn or negedge dpllclrIntData[7])
begin
if(!GLOBE_RESETn)
begin
dpllintState [7] = 1'b1;
end
else if (!dpllclrIntData[7])
begin
dpllintState [7] = 1'b1;
end
else
dpllintState [7] = 1'b0;
end
assign dpllstatechangeInt = &(dpllintState | dpllIntMask);
assign M_IRQ5n = dpllstatechangeInt;
assign dpllctlregcs = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (!M_ADDR[28]) | (M_ADDR[29]) | (M_ADDR[30]) | (!M_ADDR[31]);
myreg dpllctlReg1(
.data(M_DATA),
.csn(dpllctlregcs),
.wen(M_WEn),
.oen(M_OEn),
.rgValue(dpllctlreg),
.rstn(GLOBE_RESETn)
);
assign DPLL_TCLR = dpllctlreg[0];
assign DPLL_MUXSEL = dpllctlreg[1];
assign DPLL_FLOCK = dpllctlreg[2];
assign DPLL_MODEL1 = ~dpllctlreg[3];
assign DPLL_MODEL0 = dpllctlreg[4];
assign DPLL_RESET = dpllctlreg[5];
/*TSI CTL TSI_ODE TSI_RESETn */
assign TSI_ODE = dpllctlreg[6];
assign BITS_THZ = ~dpllctlreg[7];
assign TSI_RESETn = GLOBE_RESETn;
assign BITS_RESET = GLOBE_RESETn;
/*************************************************************************************/
/* front Panel FP_LED1/FP_LED2 MR_IN ALM_OFF()*/
/* FP_LED1 : 125mS period : startup
1S period : ok
off/on : alarm
FP_LED2 : on : master
off : slave
1S period : Write Flash
*/
wire frontpanelctlregcs;
wire [0:7] frontpanelctlreg;
assign frontpanelctlregcs = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (!M_ADDR[28]) | (!M_ADDR[29]) | (M_ADDR[30]) | (M_ADDR[31]);
myreg frontpanelctlReg1(
.data(M_DATA),
.csn(frontpanelctlregcs),
.wen(M_WEn),
.oen(M_OEn),
.rgValue(frontpanelctlreg),
.rstn(GLOBE_RESETn)
);
assign FP_LED1 = frontpanelctlreg[0];
assign FP_LED2 = frontpanelctlreg[1];
/*****************************************************************************************/
/* Switch Control :SW_ESK,SW_EDI,SW_ECS1,SW_EDO */
/* SW_EDI : from switch adm6999 to Mpc8247 */
/* SW_EDO : from mpc8247 to adm6999 */
/* SW_ESK : from mpc8247 to adm6999 */
/* SW_ECS : from mpc8247 to adm6999 */
/*****************************************************************************************/
wire switchctlreg1Cs;
wire switchctlreg2Cs;
wire [0:7] switchctl1reg;
wire [0:7] switchctl2reg;
assign switchctlreg1Cs = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (!M_ADDR[28]) | (!M_ADDR[29]) | (M_ADDR[30]) | (!M_ADDR[31]);
assign switchctlreg2Cs = M_CS7n | M_ADDR_ALL| (M_ADDR[27])
| (!M_ADDR[28]) | (!M_ADDR[29]) | (!M_ADDR[30]) | (M_ADDR[31]);
myreg switchCtlReg1(
.data(M_DATA),
.csn(switchctlreg1Cs),
.wen(M_WEn),
.oen(M_OEn),
.rgValue(switchctl1reg),
.rstn(GLOBE_RESETn)
);
myextreg switchCtlReg2(
.data(M_DATA),
.csn(switchctlreg2Cs),
.oen(M_OEn),
.mem(switchctl2reg)
);
assign switchctl2reg[0] = SW_EDO; /*pull up */
assign SW_EDI = switchctl1reg[0];
assign SW_ESK = ~switchctl1reg[1];
assign SW_ECS = switchctl1reg[2];
assign SW_RESETn = GLOBE_RESETn; /* pull down */
endmodule
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