idt723641.v

idt的双口ram的读写接口程序

assign csal = CSANeg_ipd;
assign ena = ENA_ipd;
assign wrla = WRA_ipd;
assign mba = MBA_ipd;
assign y1 = Y1;
assign AFNegint = afla;
reg ira_in,irb_in,ira_old,ff1l_a,fflgen_a;
reg irhdl1_lchd_a;
reg ff1l_b,fflgen_b;
reg irhdl1_lchd_b;
reg fs0_reg,fs1_reg,spml,pp_end,sp_end,palcntl,sercntl,irhdl2,irhdl1;
reg  aflgen_b,en_irb,en2_irb, counter1_irb ,counter2_irb,eql_orb;
wire fs0sd,fs1senl,befwftl;
//assign spml = SPMNeg_ipd;
assign fs0sd = FS0SD_ipd;
assign  fs1senl=FS1SEN_ipd;
// assign befwftl = BEFWFT_ipd;
assign befwftl = 1'b0;
reg   rcven_ae_a_old,  bcmpen_ae_a, rcven_ae_a;
reg ora_old,ef2l_a_old;
wire  unienl;     
reg  aelgen_a,eflgen_a;
reg [SizeReg:0]  aep_a;
assign unienl =1'b1;
reg bcmpen_af_b,rcven_af_b;
reg [SizeReg:0]  afp_b;
wire  csbl,enb,wlrb,mbb,bm,size; 
assign csbl = CSBNeg_ipd;
assign enb = ENB_ipd;
assign wlrb = WRB_ipd;
assign mbb = MBB_ipd;
assign bm = 1'b0;   // BM_ipd;
reg   aelb, aelb_old, ae1l_b, rcven_ae_b_old,  bcmpen_ae_b, rcven_ae_b,
      ae2la_b, orb_b2;
reg orb_old,ef2l_b_old,aften_ae_b_old,aften_ae_b,bmaft_orb;
reg  aelgen_b,eflgen_b;
reg bmaft_reg1, bmaft_reg2, bmaft_reg3,reseting1;
reg [SizeReg:0]  aep_b, rdpone_orb;
wire [SizeReg-1:0] x1;
reg counter1_orb,counter2_orb;
reg en_orb, en2_orb;
reg eq_orb, eql_orb_old;
assign x1 = X1;
assign AENegint = aelb;
integer sd_counter,counter_bm_r1,bm_r1;
 
always @(fs0_reg or fs1_reg or mrstl1 or pp_end or sp_end)
begin
    spml    = ~(~fs0_reg && ~fs1_reg ); 
    spml = 1'b1;  //?
    palcntl = ~(~fs0_reg && ~fs1_reg && spml && mrstl1 && pp_end);
    sercntl = ~(~fs0_reg && fs1_reg && ~spml && mrstl1 && sp_end);
    irhdl2 = ~(~fs0_reg && ~fs1_reg && palcntl)
	       && ~(~fs0_reg && fs1_reg && ~spml && sercntl);
    irhdl1 = ~(~fs0_reg && fs1_reg && ~spml && sercntl);
end
   
always @(mrstl1 or fs0sd or fs1senl)
begin
    if (mrstl1 == 1'b0)   fs0_reg = fs0sd;
    if (mrstl1 == 1'b0)   fs1_reg = fs1senl;
end 
always @(negedge mrstl1)       // begin reset
begin
 //       befwftl = 1'b0;  //?
        counter_bm_r1 = 0;
	reseting1 = 1'b1;
	pp_end = 1'b0;
  	sp_end = 1'b0;
       	fflgen_a = 1'b0;
	eflgen_b = 1'b0;
	afla = 1'b1;
        af1l_a = 1'b1;
        aelb = 1'b0;
        ae1l_b = 1'b0;
	rcven_ae_b = 1'b0;
	w1_ptr=0;r1_ptr=0;
        @(posedge CLKA_ipd);@(posedge CLKA_ipd);
        @(posedge CLKA_ipd);@(posedge CLKA_ipd);
        @(posedge mrstl1)  #5 reseting1 = 1'b0;
end
always @(posedge mrstl1)   // reset fs1 and fs0 =0 : 4 clocks and two clocks
begin
 //    befwftl = 1'b1;    //?
    if ((fs1_reg == 1'b0) && (fs0_reg == 1'b0))
    begin
	no_inc_w1 = 1'b1;
	@(posedge CLKA_ipd);@(posedge CLKA_ipd);
	if (unienl == 1'b1)
	begin
	    @(posedge CLKA_ipd); @(posedge CLKA_ipd);
	end
	no_inc_w1 = 1'b0;
//	if (wrla == 1'b1)
//	begin
	    pp_end = 1'b1;
//	end
    end
end
always @(posedge mrstl1 )
begin
//   tSKEW1 = 0;
//   tSKEW2 =0;
  if (reseting1 == 1'b1) 
  begin

    if ((fs1_reg == 1'b0) && (fs0_reg == 1'b0)) 
    fs1_reg = fs1_reg;// clka4 ==1
      else if ((fs1_reg == 1'b0) && (fs0_reg == 1'b0) && (spml == 1'b1))
    begin
	/* parallel programming mode */ 
	if ((mrstl1 == 1'b0)) @(posedge mrstl1);
	no_inc_w1 = 1'b1;	
	@(posedge CLKA_ipd);
	@(posedge CLKA_ipd);
	@(posedge CLKA_ipd);//   y1 = f1_in;
	@(posedge CLKA_ipd);//   x1 = f1_in;
	if (unienl == 1'b1)
	begin
	    @(posedge CLKA_ipd);//   y2 = f1_in;
	    @(posedge CLKA_ipd);//   x2 = f1_in;
	end
	no_inc_w1 = 1'b0;
        pp_end = 1'b1;
    end
    else if (spml == 1'b1)
    begin      			/* preset values */
      no_inc_w1 = 1'b0;
    end
   
    else if ((fs1_reg == 1'b1) && (fs0_reg == 1'b0) && (spml == 1'b0))
    begin
	if ((mrstl1 == 1'b0)) @(posedge mrstl1);
	no_inc_w1 = 1'b1;
	for (sd_counter=SizeReg - 1;sd_counter >= 0;sd_counter=sd_counter-1)
	begin
	    @(posedge CLKA_ipd)
	    if (fs1senl == 1'b0)
		;//y1[sd_counter] = fs0sd;
	    else
		sd_counter=sd_counter+1;
	end
	for (sd_counter=SizeReg - 1;sd_counter >= 0;sd_counter=sd_counter-1)
	begin
	    @(posedge CLKA_ipd)
	    if (fs1senl == 1'b0)
		;//x1[sd_counter] = fs0sd;
	    else
		sd_counter=sd_counter+1;
	end
	if (unienl == 1'b1)
	begin
	  for (sd_counter=SizeReg - 1;sd_counter >= 0;sd_counter=sd_counter-1)
	  begin
	    @(posedge CLKA_ipd)
	    if (fs1senl == 1'b0)
		;//y2[sd_counter] = fs0sd; 
	    else
		sd_counter=sd_counter+1;
	  end
	  for (sd_counter=SizeReg - 1;sd_counter >= 0;sd_counter=sd_counter-1)
	  begin
	    @(posedge CLKA_ipd)
	    if (fs1senl == 1'b0)
		;//x2[sd_counter] = fs0sd;
	    else
		sd_counter=sd_counter+1;  /* set counter back for next try */
	  end
	end
	no_inc_w1 = 1'b0;
	sp_end = 1'b1;
    end
  end
end

   
/* AFLA */

always @( posedge CLKA_ipd) begin
    if (CSANeg_ipd==0 && WRA_ipd==1 && ENA_ipd == 1 && MBA_ipd==0)
         if (IRint &&( state == `IDLE) && RSTNeg_ipd) // write to FIFO  
            // YAT 06/11/99 added 
        if (!RETRMODE &&!(( CountWords == 0) && FirstTime))     // for IRA set 0
                    pp_inp =0;                                      //
   if (!CSANeg_ipd && WRA_ipd && ENA_ipd && !MBA_ipd && IRint &&
                 (state == `ParProg )) 
             begin pp_inp = 1;end                                      

    if ((ira == 1'b1) && (csal == 1'b0) && (wrla == 1'b1)
	&& (mba == 1'b0) && (ena == 1'b1) && ((mrstl1 == 1'b1) ))
    begin
	if ((no_inc_w1 == 1'b0) && (pp_inp == 1'b0))
	begin
	    w1_ptr = w1_ptr + 1;
	end
    end
    ira_old = ira;
    if (((csal == 1'b0) && (wrla == 1'b1) 
	&& (mba == 1'b0) && (ena == 1'b1) && ((mrstl1 == 1'b1) )
	&& (ira == 1'b1) && (irhdl1 == 1'b1))
	|| (ira == 1'b0) || ((mrstl1 == 1'b0)))
    begin
	ira = ira_in;IRint <= ira;
    end
    if (((csal == 1'b0) && (wrla == 1'b1)
	&& (mba == 1'b0) && (ena == 1'b1) && ((mrstl1 == 1'b1) )
	&& (ira_old == 1'b1) && (irhdl1 == 1'b1))
	|| ((ira_old == 1'b0) || (ff1l_a == 1'b0))
	|| ((mrstl1 == 1'b0) ))
    begin
	ff1l_a = fflgen_a;
    end
    
 /* AFLA */   
    
    afla_old = afla;
    if ((mrstl1 == 1'b0) )
	afla = 1'b1;
    else if ((mrstl1 == 1'b0)  || ((afla == 1'b0) || (rcven_af_a == 1'b1))
	     || ((~csal && ena && wrla && ~mba && ira) && (irhdl2 == 1'b1)))
	afla = af1l_a;

    if ((bcmpen_af_a == 1'b1) && (afla_old !== af1l_a) && ((mrstl1 == 1'b1) ))
	rcven_af_a = 1'b1;
    else
	rcven_af_a = 1'b0;

    af2la_a = ~(~afla || rcven_af_a);

    af_a = y1 + w1_ptr;

    if ((mrstl1 == 1'b0) )
	af1l_a = 1'b1;
    else if (((mrstl1 == 1'b0) || ((afla_old == 1'b0) || (af1l_a == 1'b0)) 
	     || ((~csal && ena && wrla && ~mba && ira) && (irhdl2 == 1'b1)))
	     && (irhdl2 == 1'b1))
	af1l_a = aflgen_a;
    end

always @(y1 or w1_ptr or af1l_a or af2la_a)
    afp_a = y1 + w1_ptr + af1l_a + af2la_a;

always @(af_a or r1_ptr)
begin
    if ((r1_ptr[0] == af_a[0]) && (r1_ptr[1] == af_a[1]))
	bcmpen_af_a = 1'b1;
    else
	bcmpen_af_a = 1'b0;
end
always @(r1_ptr or afp_a or irhdl2 or r1_ptr_retr)
begin
    if (irhdl2 == 1'b0)
	aflgen_a = 1'b1;
    else if (((w1_ptr[SizeReg] !== afp_a[SizeReg]) || 
                   (r1_ptr_retr[SizeReg] !== afp_a[SizeReg]))
	     && ((r1_ptr_retr[SizeReg - 1:0] <= afp_a[SizeReg-1:0]) 
 		 || ((w1_ptr[SizeReg] !== afp_a[SizeReg]) &&
         (r1_ptr_retr[SizeReg] == afp_a[SizeReg]))))
	aflgen_a = 1'b0;
    else
	aflgen_a =#tSKEW2 1'b1;
//        aflgen_a = 1'b1;
end
// new for IDT723644
// for ira
always @(posedge CLKA_ipd or negedge mrstl1 or negedge prstl1)
begin
    if ((mrstl1 == 1'b0) )
	#1 irhdl1_lchd_a = irhdl1;
    else if (((csal == 1'b0) && (wrla == 1'b1) 
	&& (mba == 1'b0) && (ena == 1'b1) && ((mrstl1 == 1'b1) )
	&& (ira == 1'b1) && (irhdl1 == 1'b1))
	|| (ira == 1'b0) || ((mrstl1 == 1'b0) )) 
    begin
	irhdl1_lchd_a = irhdl1;
    end	
end

always @(irhdl1_lchd_a or fflgen_a or ff1l_a)
begin
    if (irhdl1_lchd_a == 1'b0)
	ira_in = fflgen_a;
    else if (irhdl1_lchd_a == 1'b1)
	ira_in = ff1l_a;
end
always @(w1_ptr or ira or ff1l_a)
  wtp_1 = w1_ptr + ira + ff1l_a;
    
always @(wtp_1 or r1_ptr or irhdl1 or mrstl1)
begin
    if ( RETRMODE) r1_ptr_retr =  ChadowReadPoint_ptr; else 
     r1_ptr_retr = r1_ptr;
    if ((irhdl1 == 1'b0) || (mrstl1 == 1'b0) )
	fflgen_a = 1'b0;
    else if ((wtp_1[SizeReg-1:0] == r1_ptr_retr[SizeReg-1:0])
 	     && (wtp_1[SizeReg] !== r1_ptr_retr[SizeReg]))
	fflgen_a = 1'b0;
    else
	fflgen_a = 1'b1;
end

//always @(w1_ptr or ira or ff1l_a)
//    wtp_1 = w1_ptr + ira + ff1l_a;

 // end for AELA from IDT ( 25 august) 
 
 // begin for AFB flag from IDT ( 31 august)

always @(posedge CLKB_ipd)
begin
if (bm == 1'b0)	bm_r1 = 0;
end	

///////////////////////////////////////////////////////////////////////////////
//   begin work for AEB flag ( 31 august)

  always @(posedge CLKB_ipd) 
begin 
   aften_ae_b_old = aften_ae_b;
   orb_old = orb;
  if ((en_orb == 1'b1) && (en2_orb == 1'b1) && ((bm == 1'b0)
    || (bmaft_orb == 1'b0)) 
	|| ((csbl == 1'b0) && (wlrb == 1'b1) && (mbb == 1'b0) && (enb == 1'b1)
	&& (befwftl == 1'b0) && (orb == 1'b1) && (ef2l_b == 1'b0) && (eq_orb == 1'b1))
	|| (orb == 1'b0) 
	|| ((mrstl1 == 1'b0) ))
    begin
	if (befwftl == 1'b0)
   	    orb = ef2l_b;
	else
 	    orb =  ef1l_b;
    end
    
     ef2l_b_old = ef2l_b;
    if (eql_orb == 1'b0)
	ef2l_b = 1'b0;
    else if ((en_orb == 1'b1) && (en2_orb == 1'b1) && ((bm == 1'b0)
    || (bmaft_orb == 1'b0)) 
	|| ((orb_old == 1'b0) || (ef2l_b == 1'b0))
	|| ((mrstl1 == 1'b0) ))
    begin
	ef2l_b = ef1l_b;
    end

    if (eql_orb_old == 1'b0)
	ef1l_b = 1'b0;
    else if ((en_orb == 1'b1) && (en2_orb == 1'b1) && ((bm