idt723641.v

idt的双口ram的读写接口程序

       specparam    thold_FS1SEN_CLKA_posedge    = 1;              // tSDH
       
       specparam         tpd_SIZ0_B8= 1; 
       specparam         tpd_SIZ1_B8= 1; 
       specparam         tpd_RSTNeg_EFNeg= 1; 
      // specparam         tpd_RSTNeg_AFNeg= 1; 
       specparam         tpd_SIZ0_PEFBNeg = 1;       
       specparam         tpd_SIZ1_PEFBNeg = 1;       
       specparam         tpd_ODDEVEN_B8 = 1;      
       specparam         tpd_SIZ0_B0  = 1;       
       specparam         tpd_SIZ1_B0  = 1;
    
///////////////////////////////////////////////////////////////////////////////
// Input Port  Delays   don't require Verilog description
////////////////////////////////////////////////////////////////////////////////
// Path delays                                                                //
////////////////////////////////////////////////////////////////////////////////
   
   (RSTNeg*> AFNeg)  = tpd_RSTNeg_AFNeg;
   (RSTNeg*> AENeg)  = tpd_RSTNeg_AENeg;

   (CLKA *> IR )   = tpd_CLKA_IR;  
   (CLKB *> ORB )   = tpd_CLKB_ORB; 
   
   (CLKB *> AENeg )   = tpd_CLKB_AENeg;  
   (CLKA *> AFNeg )   = tpd_CLKA_AFNeg;  
   
   (CLKA *> MBF1Neg )  = tpd_CLKA_MBF1Neg; 
   (CLKA *> MBF2Neg )  = tpd_CLKA_MBF2Neg; 
   (CLKB *> MBF1Neg )  = tpd_CLKB_MBF1Neg; 
   (CLKB *> MBF2Neg )  = tpd_CLKB_MBF2Neg;//??
 
 (CLKB *> B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,
          B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31,B32,B33,B34,B35 )
          = tpd_CLKB_B0;
   
(CLKB *> A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,A16,A17,A18,
         A19,A20,A21,A22,A23,A24,A25,A26,A27,A28,A29,A30,A31,A32,A33,A34,A35 )
         = tpd_CLKB_A0;

(CLKA *> B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,
         B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31,B32,B33,B34,B35 )
         = tpd_CLKA_B0;
    
(CSANeg *> A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,A16,A17,A18,
           A19,A20,A21,A22,A23,A24,A25,A26,A27,A28,A29,A30,A31,A32,A33,A34,A35 )
           = tpd_CSBNeg_A0;

(CSBNeg *> B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,
           B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31,B32,B33,B34,B35 )
           = tpd_CSBNeg_B0;
     
(MBB *> B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,
        B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31,B32,B33,B34,B35 )
        = tpd_MBB_B0;
       
(WRA *> A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,A16,A17,A18,A19,
        A20,A21,A22,A23,A24,A25,A26,A27,A28,A29,A30,A31,A32,A33,A34,A35 )
        = tpd_CSBNeg_A0;
          
    // net        
(WRB *> B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12,B13,B14,B15,B16,B17,B18,B19,
        B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31,B32,B33,B34,B35 )
        = tpd_MBB_B0;
     
////////////////////////////////////////////////////////////////////////////////
// Timing Violation
////////////////////////////////////////////////////////////////////////////////
    // CLK period checking
    
        $period (posedge CLKA, tpw_CLKA);
        $period (posedge CLKB, tpw_CLKB);
       
   // CLKA pulse width check(high & low)
   
        $width ( posedge CLKA, tpw_CLKA_posedge);
        $width ( negedge CLKA, tpw_CLKA_negedge);
        // VitalPeriodPulseCheck ( TestSignal      => CLKA,...
                                               
   // CLKB pulse width check(high & low)

        $width ( posedge CLKB, tpw_CLKB_posedge);
        $width ( negedge CLKB, tpw_CLKB_negedge);
        // VitalPeriodPulseCheck ( TestSignal      => CLKB,...
      
    // A/CLKA setup/hold time check
    
     $setuphold ( posedge CLKA &&& Check2, A0,   
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A1,   
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A2,   
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A3,   
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A4,   
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A5,   
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A6,   
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A7,   
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A8,   
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A9,   
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A10,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A11,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A12,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A13,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A14,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A15,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A16,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A17,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A18,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A19,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A20,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A21,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A22,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A23,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A24,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A25,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A26,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A27,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A28,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A29,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A30,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A31,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A32,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A33,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A34,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);  
     $setuphold ( posedge CLKA &&& Check2, A35,  
                  tsetup_A0_CLKA_posedge, thold_A0_CLKA_posedge);
      
       // B/CLKB setup/hold time check
    
     $setuphold ( posedge CLKB &&& Check1, B0,   
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B1,   
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B2,   
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B3,   
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B4,   
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B5,   
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B6,   
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B7,   
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B8,   
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B9,   
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B10,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B11,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B12,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B13,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B14,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B15,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B16,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B17,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B18,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B19,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B20,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B21,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B22,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B23,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B24,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B25,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B26,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B27,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B28,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B29,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B30,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B31,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B32,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B33,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B34,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);  
     $setuphold ( posedge CLKB &&& Check1, B35,  
                  tsetup_B0_CLKB_posedge, thold_B0_CLKB_posedge);
      
      // ENA/CLKA setup/hold time check

        $setuphold ( posedge CLKA, ENA,  
                     tsetup_ENA_CLKA_posedge,thold_ENA_CLKA_posedge);   

        $setuphold ( posedge CLKB, ENB,  
                     tsetup_ENB_CLKB_posedge,thold_ENB_CLKB_posedge);   
                       
     // CSBNeg/CLKB setup/hold time check
   
        $setuphold ( posedge CLKB, CSBNeg,  
                     tsetup_CSBNeg_CLKB_posedge, thold_CSBNeg_CLKB_posedge);   
        $setuphold ( posedge CLKA, CSANeg,  
                     tsetup_CSANeg_CLKA_posedge, thold_CSANeg_CLKA_posedge);
        
       // WRA/CLKA setup/hold time check

        $setuphold ( posedge CLKA, WRA,  
                     tsetup_WRA_CLKA_posedge,thold_WRA_CLKA_posedge);
     
       $setuphold ( posedge CLKB, WRB,  
                     tsetup_WRB_CLKB_posedge,thold_WRB_CLKB_posedge);
       
       // MBA/CLKA setup/hold time check

         $setuphold ( posedge CLKA, MBA,  
                     tsetup_MBA_CLKA_posedge,thold_MBA_CLKA_posedge);
           
         $setuphold ( posedge CLKB, MBB,  
                     tsetup_MBB_CLKB_posedge,thold_MBB_CLKB_posedge);
                          
        //  RFM,RTM setup/hold time check i podpravit RESET i td!!!!!!!!!!!!!!!
        
         $setuphold ( posedge CLKB, RFM,  
                     tsetup_RFM_CLKB_posedge,thold_RFM_CLKB_posedge);   
         $setuphold ( posedge CLKB, RTM,  
                     tsetup_RTM_CLKB_posedge,thold_RTM_CLKB_posedge);
         
        //RSTNeg/CLKA    

         $setuphold ( posedge CLKA, RSTNeg,  
                     tsetup_RSTNeg_CLKA_posedge,thold_RSTNeg_CLKA_posedge);   
         $setuphold ( posedge CLKB, RSTNeg,  
                     tsetup_RSTNeg_CLKB_posedge,thold_RSTNeg_CLKB_posedge);   
         
         //RSTNeg/FS0SD
       
         $setuphold ( posedge RSTNeg, FS0SD,  
                     tsetup_FS0SD_RSTNeg_posedge,thold_FS0SD_RSTNeg_posedge);
         $setuphold ( posedge RSTNeg, FS1SEN, 
                     tsetup_FS1SEN_RSTNeg_posedge,thold_FS1SEN_RSTNeg_posedge);
           
        //  FS0SD, FS1SEN/ CLKA  setup/hold time check
  
        $setuphold ( posedge CLKA, FS0SD,  
                     tsetup_FS0SD_CLKA_posedge, thold_FS0SD_CLKA_posedge);
        $setuphold ( posedge CLKA, FS1SEN,  
                     tsetup_FS1SEN_CLKA_posedge, thold_FS1SEN_CLKA_posedge);
  
// Signal
                       
    endspecify     
         
 ////////////////////////////////////////////////////////////////////////////////
// Main Behavior Block                                                        //
////////////////////////////////////////////////////////////////////////////////

// instead of A0, B0, ..... for behavior you should use:
//    - A0in, B0in ( in any expressions),
//    -  A0out, B0out - in left-hand parts of assignment statements

  reg [OffsetLength -1:0] X1, Y1; // AlFull-AlEmpty Offset regs
  reg [35 : 0] Mail1, Mail2, Mailout1, Mailout2, OutReg, ChadowOutReg, OutReg1,
               Aux1,FWTTreg;     
   time tSKEW1, tSKEW2;     // min tSKEW vals to be       
  reg [OffsetLength:0] WritePoint, ReadPoint,ChadowReadPoint,FW;
  reg [OffsetLength:0] CountWords ,ChadowCountWords,CountWords_P;
  
  reg  ef2l_a, ef1l_a,ef2l_b ,ef1l_b, read_b_enable, pp_inp,ORB2L;
  reg [SizeReg:0] rdp_2,rdp_1,r1_shadow;
  reg [SizeReg:0] af_a, ae_a, af_b, ae_b;                         
  reg  read_a_enable;
  reg [35:0] r1,r2;   // YAT pipeline for first word -3 clka delay  
  reg [SizeReg:0] w1_ptr,ChadowReadPoint_ptr,r1_ptr;
   
  reg Viol1,Viol2, In1, In2, In3,Rd, Wr, Rd1, Wr1,SRAM2_In1,SRAM2_In3,
         FWT1,FWT2,                      // for fthowfall first word
         FWT1S,FWT2S,
         ORBPint,ORAPint,             // for delayed OR fall
         RETRMODE ,R3int,              // For RETRANSM MODE
         SW1L,SW0L, SIZ1L, SIZ0L; 
  reg RdFull, RdAlFull,WrFirstCell, WrAlEmCell, RdFull1,
       RdAlFull1,WrFirstCell1, WrAlEmCell1, Net1,Net2;
  integer ReadNo, LimitC,CountR3int, LimitB;
  reg [2:0] state;
         
   assign Check1 = !CSBNeg_ipd && !WRB_ipd && ENB_ipd && MBB_ipd;
               // signal for setup checking between CLKB and B bus
  assign Check2 = !CSANeg_ipd && WRA_ipd && ENA_ipd ;
              // signal for setup checking between CLKA and A bus
       
    `define IDLE          'b000
    `define MasterReset   'b001
    `define ParProg       'b010
    `define prX1          'b011 
    `define prY2          'b100
    `define prX2          'b101 
    `define SerProg       'b110
    
  wire  MRS1PAR,MRS2PAR;
  reg FirstTime;
  reg En, ren1,ren2; 
  
        
  always                                  //  Reset of FIFO1