idt723641.v

idt的双口ram的读写接口程序

     FS0SD_ipd,FS1SEN_ipd;
                    
 wire RST1Neg_ipd ;  
 
wire WRA_ipd;
wire WRB_ipd;
wire  A0_ipd, Check1,Check2;  
   
 wire [35: 0] B_ipd; //? 
                    
   // buffers for qualifying all inputs for MIPD
 
 buf   (RSTNeg_ipd,RSTNeg);
  
 buf   (A0in, A0);
 buf   (A1in, A1);
 buf   (A2in, A2);
 buf   (A3in, A3);
 buf   (A4in, A4);
 buf   (A5in, A5);
 buf   (A6in, A6);
 buf   (A7in, A7);
 buf   (A8in, A8);
 buf   (A9in, A9);
 buf   (A10in, A10);
 buf   (A11in, A11);
 buf   (A12in, A12);
 buf   (A13in, A13);
 buf   (A14in, A14);
 buf   (A15in, A15);
 buf   (A16in, A16);
 buf   (A17in, A17);
 buf   (A18in, A18);
 buf   (A19in, A19);
 buf   (A20in, A20);
 buf   (A21in, A21);
 buf   (A22in, A22);
 buf   (A23in, A23);
 buf   (A24in, A24);
 buf   (A25in, A25);
 buf   (A26in, A26);
 buf   (A27in, A27);
 buf   (A28in, A28);
 buf   (A29in, A29);
 buf   (A30in, A30);
 buf   (A31in, A31);
 buf   (A32in, A32);
 buf   (A33in, A33);
 buf   (A34in, A34);
 buf   (A35in, A35);
 
 buf   (B0in, B0);
 buf   (B1in, B1);
 buf   (B2in, B2);
 buf   (B3in, B3);
 buf   (B4in, B4);
 buf   (B5in, B5);
 buf   (B6in, B6);
 buf   (B7in, B7);
 buf   (B8in, B8);
 buf   (B9in, B9);
 buf   (B10in, B10);
 buf   (B11in, B11);
 buf   (B12in, B12);
 buf   (B13in, B13);
 buf   (B14in, B14);
 buf   (B15in, B15);
 buf   (B16in, B16);
 buf   (B17in, B17);
 buf   (B18in, B18);
 buf   (B19in, B19);
 buf   (B20in, B20);
 buf   (B21in, B21);
 buf   (B22in, B22);
 buf   (B23in, B23);
 buf   (B24in, B24);
 buf   (B25in, B25);
 buf   (B26in, B26);
 buf   (B27in, B27);
 buf   (B28in, B28);
 buf   (B29in, B29);
 buf   (B30in, B30);
 buf   (B31in, B31);
 buf   (B32in, B32);
 buf   (B33in, B33);
 buf   (B34in, B34);
 buf   (B35in, B35);

 buf   (CLKB_ipd, CLKB);
 buf   (CLKA_ipd, CLKA);   
    
 buf   (CSANeg_ipd, CSANeg );
 buf   (CSBNeg_ipd, CSBNeg );
 buf   (ENA_ipd, ENA);
 buf   (ENB_ipd, ENB);
 
 buf   (MBA_ipd, MBA);
 buf   (MBB_ipd, MBB);  
    
 buf   (WRA_ipd, WRA);
 buf   (WRB_ipd, WRB);
 
 buf (FS0SD_ipd,FS0SD);
 buf (FS1SEN_ipd,FS1SEN);
 
 buf   (RTM_ipd,RTM );
 buf   (RFM_ipd,RFM );  

   // buffers for qualifying all outputs as accelerated nets    
 
 buf (AENeg, AENegint);
 buf (AFNeg, AFNegint);

 buf (MBF1Neg, MBF1Negint);
 buf (MBF2Neg, MBF2Negint);
 
 buf (ORB,ORBint);
 buf (IR,IRint);
 
 nmos   (A0,   A0out, 1);
 nmos   (A1,   A1out, 1);
 nmos   (A2,   A2out, 1);
 nmos   (A3,   A3out, 1);
 nmos   (A4,   A4out, 1);
 nmos   (A5,   A5out, 1);
 nmos   (A6,   A6out, 1);
 nmos   (A7,   A7out, 1);
 nmos   (A8,   A8out, 1);
 nmos   (A9,   A9out, 1);
 nmos   (A10, A10out, 1);
 nmos   (A11, A11out, 1);
 nmos   (A12, A12out, 1);
 nmos   (A13, A13out, 1);
 nmos   (A14, A14out, 1);
 nmos   (A15, A15out, 1);
 nmos   (A16, A16out, 1);
 nmos   (A17, A17out, 1);
 nmos   (A18, A18out, 1);
 nmos   (A19, A19out, 1);
 nmos   (A20, A20out, 1);
 nmos   (A21, A21out, 1);
 nmos   (A22, A22out, 1);
 nmos   (A23, A23out, 1);
 nmos   (A24, A24out, 1);
 nmos   (A25, A25out, 1);
 nmos   (A26, A26out, 1);
 nmos   (A27, A27out, 1);
 nmos   (A28, A28out, 1);
 nmos   (A29, A29out, 1);
 nmos   (A30, A30out, 1);
 nmos   (A31, A31out, 1);
 nmos   (A32, A32out, 1);
 nmos   (A33, A33out, 1);
 nmos   (A34, A34out, 1);
 nmos   (A35, A35out, 1);
  
  
 nmos   (B0,   B0out, 1);
 nmos   (B1,   B1out, 1);
 nmos   (B2,   B2out, 1);
 nmos   (B3,   B3out, 1);
 nmos   (B4,   B4out, 1);
 nmos   (B5,   B5out, 1);
 nmos   (B6,   B6out, 1);
 nmos   (B7,   B7out, 1);
 nmos   (B8,   B8out, 1);
 nmos   (B9,   B9out, 1);
 nmos   (B10, B10out, 1);
 nmos   (B11, B11out, 1);
 nmos   (B12, B12out, 1);
 nmos   (B13, B13out, 1);
 nmos   (B14, B14out, 1);
 nmos   (B15, B15out, 1);
 nmos   (B16, B16out, 1);
 nmos   (B17, B17out, 1);
 nmos   (B18, B18out, 1);
 nmos   (B19, B19out, 1);
 nmos   (B20, B20out, 1);
 nmos   (B21, B21out, 1);
 nmos   (B22, B22out, 1);
 nmos   (B23, B23out, 1);
 nmos   (B24, B24out, 1);
 nmos   (B25, B25out, 1);
 nmos   (B26, B26out, 1);
 nmos   (B27, B27out, 1);
 nmos   (B28, B28out, 1);
 nmos   (B29, B29out, 1);
 nmos   (B30, B30out, 1);
 nmos   (B31, B31out, 1);
 nmos   (B32, B32out, 1);
 nmos   (B33, B33out, 1);
 nmos   (B34, B34out, 1);
 nmos   (B35, B35out, 1);
   
 specify

        // tipd delays: interconnect path delays , mapped to input port delays.
        // In Verilog is not necessary to declare any tipd_ delay variables,
        // they can be taken from SDF file
        // With all the other delays real delays would be taken from SDF file
        // tpd delays: propagation delays
     specparam           tpd_CLKA_A0           =1;
     specparam           tpd_CLKA_FFNeg        =1;  // tWFF  //????
     specparam           tpd_CLKB_EFNeg        =1;  // tREF
     specparam           tpd_CLKB_PEFBNeg      =1;  // tPPE
     specparam           tpd_CLKB_AENeg        =1;  // tPAE
     specparam           tpd_CLKA_AFNeg        =1;  // tPAF
     specparam           tpd_CLKA_MBF1Neg      =1;  // tPMF
     specparam           tpd_CLKA_MBF2Neg      =1;  // tPMF
     specparam           tpd_CLKB_MBF1Neg      =1;  // tPMF
     specparam           tpd_CLKB_MBF2Neg      =1;  // tPMF
     specparam           tpd_CLKA_B0           =1;  // tPMR
     
     specparam           tpd_CLKA_IR     	=1;  // tPIR
     specparam           tpd_CLKB_ORB     	=1;  // tPOR
     
     specparam           tpd_CLKB_A0           =1;  // tPMR
     specparam           tpd_CLKB_B0           =1;  // tA     //???
     specparam           tpd_A0_PEFANeg        =1;  // tPDPE
     specparam           tpd_B0_PEFBNeg        =1;  // tPDPE
     specparam           tpd_ODDEVEN_PEFANeg   =1;  // tPOPE
     specparam           tpd_ODDEVEN_PEFBNeg   =1;           // tPOPE
     specparam           tpd_ODDEVEN_ParityBits =1;        // tPOPB
     specparam           tpd_CSANeg_PEFANeg    =1;   // tPEPE
     specparam           tpd_ENA_PEFANeg       =1;   // tPEPE
     specparam           tpd_WRA_PEFANeg       =1;   // tPEPE
     specparam           tpd_MBA_PEFANeg       =1;   // tPEPE
     specparam           tpd_PGA_PEFANeg       =1;   // tPEPE
     specparam           tpd_CSBNeg_PEFBNeg    =1;   // tPEPE
     specparam           tpd_ENB_PEFBNeg       =1;   // tPEPE
     specparam           tpd_WRB_PEFBNeg       =1;   // tPEPE
    
     specparam           tpd_PGB_PEFBNeg       =1;   // tPEPE
     specparam           tpd_RSTNeg_AENeg      =1;   // tRSF
    specparam            tpd_RSTNeg_AFNeg      =1;   // tRSF
     specparam           tpd_RSTNeg_MBF1Neg    =1;   // tRSF
     specparam           tpd_RSTNeg_MBF2Neg    =1;   // tRSF
     specparam           tpd_CSBNeg_A0         =1;   // tEN/tDIS
     specparam           tpd_WRB_A0            =1;   // tEN/tDIS
     specparam           tpd_CSBNeg_B0         =1;   // tEN/tDIS
     specparam           tpd_WRB_B0            =1;   // tEN/tDIS
     specparam           tpd_ODDEVEN_A8        =1;   // tPOPB
     specparam           tpd_WRA_A8            =1;   // tPEPB
      
     specparam           tpd_WRB_A8            =1;   // tPEPB 
     specparam           tpd_ENB_A8            =1;   // tPEPB 
     specparam           tpd_ENA_A8            =1;   // tPEPB 
     specparam           tpd_CSBNeg_A8         =1;   // tPEPB 
     specparam           tpd_CSANeg_A8         =1;   // tPEPB 
     specparam           tpd_PGA_A8            =1;   // tPEPB 
     specparam           tpd_PGB_A8            =1;   // tPEPB
     specparam           tpd_MBA_A8            =1;   // tPEPB 
     specparam           tpd_MBB_B0            =1;   // tMDV
      
                     // tpw values: pulse widths
     
     specparam           tpw_CLKA = 1;      // tCLKA
     specparam           tpw_CLKB = 1;      // tCLKB

     specparam           tpw_CLKA_posedge = 1;      // tCLKH
     specparam           tpw_CLKB_posedge = 1;      // tCLKH
     specparam           tpw_CLKA_negedge = 1;      // tCLKL
     specparam           tpw_CLKB_negedge = 1;      // tCLKL

                // tsetup values: setup times

      specparam          tsetup_A0_CLKA_posedge = 1;      // tDS
      specparam          tsetup_B0_CLKB_posedge = 1;      // tDS
      specparam          tsetup_CSANeg_CLKA_posedge = 1;             // tENS1
      specparam          tsetup_WRA_CLKA_posedge  = 1;               // tENS1
      specparam          tsetup_CSBNeg_CLKB_posedge= 1;              // tENS1
      specparam          tsetup_WRB_CLKB_posedge  = 1;               // tENS1
      specparam          tsetup_ENA_CLKA_posedge   = 1;              // tENS2
      specparam          tsetup_ENB_CLKB_posedge   = 1;              // tENS2
      specparam          tsetup_MBA_CLKA_posedge   = 1;              // tENS3
      specparam          tsetup_MBB_CLKB_posedge   = 1;             //tMDV
      
      specparam          tsetup_RSTNeg_CLKA_posedge   = 1;              // tRSTS
      specparam          tsetup_RSTNeg_CLKB_posedge   = 1;              // tRSTS
      specparam          tsetup_FS0SD_CLKA_posedge    = 1;              // tSDS
      specparam          tsetup_FS1SEN_CLKA_posedge    = 1;              // tSDS
      specparam          tsetup_SW0_CLKB_posedge   = 1;              // tFSS
      specparam          tsetup_SW1_CLKB_posedge    = 1;
      specparam          tsetup_BENeg_CLKB_posedge  = 1;      
      specparam          tsetup_SIZ1_CLKB_posedge    = 1;      
      specparam          tsetup_SIZ0_CLKB_posedge    = 1;
      specparam          tsetup_FS1SEN_RSTNeg_posedge     = 1;      
      specparam          tsetup_MRS1_CLKA_posedge   = 1;
      specparam          tsetup_MRS1_CLKB_posedge   = 1;       
      specparam          tsetup_MRS2_CLKB_posedge   = 1;              
      specparam          tsetup_PRS1_CLKA_posedge= 1;
      specparam          tsetup_PRS1_CLKB_posedge= 1;                     
      specparam          tsetup_MRS2_CLKA_posedge= 1;
      specparam          tsetup_PRS2_CLKA_posedge= 1;                 
      specparam          tsetup_PRS2_CLKB_posedge= 1;               
      specparam          tsetup_FS0sd_MRS1_posedge= 1;               
      specparam          tsetup_FS1SEN_MRS1_posedge= 1;               
      specparam          tsetup_MRS2_SPM_posedge= 1;               
      specparam          tsetup_MRS1_SPM_posedge= 1;               
      specparam          tsetup_MRS2_BEF_posedge= 1;               
      specparam          tsetup_MRS1_BEF_posedge= 1;               
      specparam          tsetup_FS0SD_RSTNeg_posedge= 1; 
    //specparam          tsetup_FS1SEN_RSTNeg_posedge= 1;
      specparam          tsetup_RTM_CLKB_posedge= 1; 
      specparam          tsetup_RFM_CLKB_posedge= 1;   //tRMS                    
                // thold values: hold times            //tRMS
                
       specparam    thold_RSTNeg_CLKB_posedge   = 1;              // tRSTS         
       specparam  	thold_RSTNeg_CLKA_posedge   = 1;              // tRSTS         
       specparam 	thold_BEF_CLKA_posedge = 1;                       
       specparam 	thold_FS1SEN_MRS2_posedge = 1;               
       specparam 	thold_FS1SEN_MRS1_posedge= 1;                
       specparam 	thold_MRS1_BEF_posedge = 1;                
       specparam 	thold_MRS2_BEF_posedge = 1;
       specparam 	thold_MRS1_CLKA_posedge = 1;                
       specparam 	thold_MRS2_CLKB_posedge = 1;                
       specparam 	thold_MRS2_CLKA_posedge= 1;                
       specparam 	thold_MRS1_CLKB_posedge= 1;                
       specparam 	thold_PRS1_CLKA_posedge= 1;                
       specparam 	thold_PRS2_CLKB_posedge= 1;                
       specparam 	thold_PRS1_CLKB_posedge= 1;                
       specparam 	thold_PRS2_CLKA_posedge= 1;                
       specparam 	thold_FS0sd_MRS1_posedge= 1;                
       specparam 	thold_FS0sd_MRS2_posedge= 1;                
       specparam 	thold_MRS1_SPM_posedge= 1;                
       specparam 	thold_MRS2_SPM_posedge= 1;                
       specparam    thold_SW0_CLKB_posedge   = 1;             
       specparam    thold_SW1_CLKB_posedge    = 1;
       specparam    thold_BENeg_CLKB_posedge  = 1;      
       specparam    thold_SIZ1_CLKB_posedge    = 1;      
       specparam    thold_SIZ0_CLKB_posedge    = 1;
       specparam    thold_A0_CLKA_posedge = 1;      // tDH
       specparam    thold_B0_CLKB_posedge = 1;      // tDH
       specparam    thold_CSANeg_CLKA_posedge = 1;  // tENH1
       specparam    thold_WRA_CLKA_posedge = 1;     // tENH1
       specparam    thold_CSBNeg_CLKB_posedge = 1;  // tENH1
       specparam    thold_WRB_CLKB_posedge = 1;     // tENH1
       specparam    thold_ENA_CLKA_posedge = 1;     // tENH2
       specparam    thold_ENB_CLKB_posedge = 1;     // tENH2
       specparam    thold_MBA_CLKA_posedge = 1;     // tENH3
       specparam    thold_MBB_CLKB_posedge = 1;     //tMDV
       specparam    thold_ODDEVEN_CLKB_posedge = 1; // tPGH
       specparam    thold_PGB_CLKB_posedge= 1;      // tPGH
       specparam    thold_RST_CLKA_posedge= 1;      // tRSTH
       specparam    thold_RST_CLKB_posedge= 1;      // tRSTH
       specparam    thold_FS0SD_RSTNeg_posedge = 1;      // tFSH
       specparam    thold_FS1SEN_RSTNeg_posedge = 1;      // tFSH
       specparam    thold_RTM_CLKB_posedge= 1;       //tRMH
       specparam    thold_RFM_CLKB_posedge= 1;        //tRMH
       specparam    thold_FS0SD_CLKA_posedge    = 1;              // tSDH