idt723641.v

idt的双口ram的读写接口程序

////////////////////////////////////////////////////////////////////////////////
//  File name : idt723641.v 
////////////////////////////////////////////////////////////////////////////////
//  Copyright (C) 1999 Integrated Device Technology; http://www.idt.com/
//  Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT
//  and supported by Free Model Foundry; http://eda.org/fmf/
//
//  This program is free software; you can redistribute it and/or modify
//  it under the terms of the GNU General Public License version 2 as
//  published by the Free Software Foundation.
//
//  This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no
//  warranty with respect to the information contained herein. IDT DISCLAIMS
//  AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING
//  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE
//  ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN
//  NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN
//  CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,
//  CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR
//  APPLICATION OF THE VHDL model. Further, IDT reserves the right to make
//  changes without notice to any product herein to improve reliability,
//  function, or design.  IDT does not convey any license under patent rights
//  or any other intellectual property rights, including those of third parties.
//  IDT is not obligated to provide maintenance or support for the licensed VHDL
//  model.
///////////////////////////////////////////////////////////////////////////////
//
//  MODIFICATION HISTORY :
//
//  version | author            | mod date | changes made
//    V1.0     Arkadi Poliakov     99 06 21 initial release
//              Y.A.T., V.V.Y.
//    V1.1     R. Munden          02 JUN 16 licensing changed to GPL
//
////////////////////////////////////////////////////////////////////////////////
//
//  PART DESCRIPTION :
//
//  Library:     FIFO
//  Technology:  CMOS
//  Part:        IDT723641
//
//  Description: SyncFIFO 1024x36 Memory
//
////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
// MODULE DECLARATION                                                         //
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ns

module IDT723641 

            (
                 A0 , 			// 36 pin Port-A data bus
                 A1 ,  
                 A2 ,   
                 A3 ,     
                 A4 ,     
                 A5 ,     
                 A6 ,      
                 A7 ,    
                 A8 ,  
                 A9 ,     
                 A10 ,     
                 A11,      
                 A12 ,    
                 A13 ,     
                 A14,    
                 A15,
                 A16,
                 A17,
                 A18,  
                 A19,
                 A20,
                 A21,
                 A22,
                 A23,
                 A24,
                 A25,
                 A26,
                 A27,
                 A28,
                 A29,
                 A30 ,
                 A31 ,
                 A32 ,
                 A33,
                 A34,
                 A35,
                 AENeg,   			//   Almost-Empty Flag
                 AFNeg,   			//   Almost-Full Flag
                 B0 ,     			//   36 pin Port-B data bus
                 B1,  
                 B2 ,
                 B3,
                 B4,
                 B5,
                 B6,
                 B7,
                 B8,
                 B9,
                 B10, 
                 B11,
                 B12,
                 B13,
                 B14,
                 B15,
                 B16,
                 B17,
                 B18,
                 B19,  
                 B20, 
                 B21,
                 B22,
                 B23,
                 B24,
                 B25,
                 B26,
                 B27, 
                 B28,
                 B29,
                 B30,
                 B31,
                 B32,
                 B33,                
                 B34, 
                 B35,   
                 CLKA,     			//   Port-A clock
                 CLKB,     			//   Port-B clock
                 CSANeg,   			// Port-A Chip Select
                 CSBNeg,   			// Port-B Chip Select

                 ENA,      			// Port-A Enable
                 ENB ,     			// Port-B Enable

			// Changed port names according to 723641
			// for FS0 and FS1, they now have dual purpose

                 FS0SD,      			// Flag Offset Select
						// and Serial Data
                 FS1SEN,      		        // Flag Offset Select
						// and Serial Enable

                 IR,	   			// Input Ready Flag

                 MBA,      			// Port-A Mailbox Select
                 MBB,      			// Port-B Mailbox Select
                 MBF1Neg , 			// Mail1 Register Flag
                 MBF2Neg , 			// Mail2 Register Flag

                 ORB,	  			// Output ready flag
                                          // Name OR not avalable in VHDL
                 RTM,
                 RFM,	  			// Read From Mark

                 RSTNeg,   			// Reset
                 WRA,     			// Port-A Write/Read Select
						// Active high Write , 
						// Active low Read
                 WRB     			// Port-B Write/Read Select
						// Active high Read ,
						// Active low Write
                );

////////////////////////////////////////////////////////////////////////
// Port / Part Pin Declarations

         inout        A0;  		// Bidirectional 36 bit Data Port A.  
         inout        A1;     
         inout        A2;
         inout        A3;
         inout        A4;
         inout        A5;
         inout        A6;
         inout        A7;
         inout        A8;
         inout        A9;
         inout        A10;
         inout        A11;
         inout        A12;
         inout        A13;
         inout        A14;
         inout        A15;
         inout        A16;
         inout        A17;
         inout        A18;  
         inout        A19;
         inout        A20;
         inout        A21;
         inout        A22;
         inout        A23;
         inout        A24;
         inout        A25;
         inout        A26;
         inout        A27;
         inout        A28;
         inout        A29;
         inout        A30;
         inout        A31;
         inout        A32;
         inout        A33;
         inout        A34;
         inout        A35;
         output       AENeg;   		//  Almost-Empty Flag
         output       AFNeg;   		//  Almost-Full Flag
         inout        B0;		// Bidirectional 36 bit Data Port B
         inout        B1;
         inout        B2;
         inout        B3;
         inout        B4;
         inout        B5;
         inout        B6;
         inout        B7;
         inout        B8;
         inout        B9;
         inout        B10;
         inout        B11;
         inout        B12;
         inout        B13;
         inout        B14;
         inout        B15;
         inout        B16;
         inout        B17;
         inout        B18;    
         inout        B19;
         inout        B20;
         inout        B21;
         inout        B22;
         inout        B23;
         inout        B24;
         inout        B25;
         inout        B26;
         inout        B27;
         inout        B28;
         inout        B29;
         inout        B30;
         inout        B31;
         inout        B32;
         inout        B33;
         inout        B34;
         inout        B35;
         input        CLKA;       		//  Port-A clock
         input        CLKB;       		//  Port-B clock
         input        CSANeg;     		//  Port-A Chip Select
         input        CSBNeg;     		//  Port-B Chip Select
         input        ENA;        		//  Port-A Enable
         input        ENB;         		// Port-B Enable
         input        FS0SD;         		// Flag Offset 0 / Serial Data
         input        FS1SEN;            	// Flag Offset Select
	
         output       IR;			// Input ready Flag
         input        MBA;         		// Port-A Mailbox Select
         input        MBB;         		// Port-B Mailbox Select
         output       MBF1Neg;     		// Mail1 Register Flag
         output       MBF2Neg;     		//   Mail2 Register Flag
         output       ORB;			// Output Ready Flag
         input 	      RFM;			// Read From Mark
         input        RSTNeg;         		// Reset
         input	      RTM;			// Retransmit Mode
         input        WRA;           // Port-A Write/Read Select
         input        WRB;           // Port-B Write/Read Select

         wire 	      IR;
         wire	      ORB;

         reg          MBF1Negint, MBF2Negint;    
         wire       AENeg, AFNeg,AENegint, AFNegint, MBF1Neg,MBF2Neg ;
         
         reg [35: 0] Aout;
         
         wire       A0out,A1out,A2out,A3out,A4out,A5out,A6out,A7out,A8out,
                    A9out,A10out,A11out,A12out,A13out,
                    A14out,A15out,A16out,A17out,A18out,A19out,A20out,A21out,
                    A22out,A23out,A24out,A25out,
                    A26out,A27out,A28out,A29out,A30out,A31out,A32out,A33out,
                    A34out,A35out ;
                    
         wire       A0in,A1in,A2in,A3in,A4in,A5in,A6in,A7in,A8in,A9in,A10in,
                    A11in,A12in,A13in,A14in,A15in,
                    A16in,A17in,A18in,A19in,A20in,A21in,A22in,A23in,A24in,A25in,
                    A26in,A27in,A28in,A29in,A30in,A31in,
                    A32in,A33in,A34in,A35in;
             
         wire [35: 0] Ain;
         assign Ain = {A35in,A34in,A33in,A32in,A31in,A30in,A29in,A28in,A27in,
                       A26in,A25in,A24in,A23in,A22in,A21in,A20in,
                       A19in,A18in,A17in,A16in,A15in,A14in,A13in,A12in,A11in,
                       A10in,A9in,A8in,A7in,A6in,A5in,A4in,
                       A3in,A2in,A1in,A0in };
         
         reg [35: 0] Bout;
         
         wire       B0out,B1out,B2out,B3out,B4out,B5out,B6out,B7out,B8out,B9out,
                    B10out,B11out,B12out,B13out,
                    B14out,B15out,B16out,B17out,B18out,B19out,B20out,B21out,
                    B22out,B23out,B24out,B25out,
                    B26out,B27out,B28out,B29out,B30out,B31out,B32out,B33out,
                    B34out,B35out ;
                    
         wire       B0in,B1in,B2in,B3in,B4in,B5in,B6in,B7in,B8in,B9in,B10in,
                    B11in,B12in,B13in,B14in,B15in,
                    B16in,B17in,B18in,B19in,B20in,B21in,B22in,B23in,B24in,B25in,
                    B26in,B27in,B28in,B29in,B30in,B31in,
                    B32in,B33in,B34in,B35in;
             
         
          wire [35: 0] Bin;
         assign Bin = {B35in,B34in,B33in,B32in,B31in,B30in,B29in,B28in,B27in,
                       B26in,B25in,B24in,B23in,B22in,B21in,B20in,
                       B19in,B18in,B17in,B16in,B15in,B14in,B13in,B12in,B11in,
                       B10in,B9in,B8in,B7in,B6in,B5in,B4in,
                       B3in,B2in,B1in,B0in };
      
          assign       {A35out,A34out,A33out,A32out,A31out,A30out,A29out,A28out,
                        A27out,A26out,A25out,A24out,A23out,A22out,A21out,A20out,
                        A19out,A18out,A17out,A16out,A15out,A14out,A13out,A12out,
                        A11out,A10out,A9out,A8out,A7out,A6out,A5out,A4out,
                        A3out,A2out,A1out,A0out } = Aout ;
                    
        assign       {B35out,B34out,B33out,B32out,B31out,B30out,B29out,B28out,
                      B27out,B26out,B25out,B24out,B23out,B22out,B21out,B20out,
                      B19out,B18out,B17out,B16out,B15out,B14out,B13out,B12out,
                      B11out,B10out,B9out,B8out,B7out,B6out,B5out,B4out,
                      B3out,B2out,B1out,B0out } = Bout ;             
                    
          parameter timingmodel = "defaulttimingmodel";            
                    
 parameter SRAMSize = 1024;
 parameter SRAMWordLength = 36;   // number of bits in SRAM word
 parameter NumBitProg = 20;  // Bit number for serial programming of X1,Y1,
 parameter OffsetLength = 10;
 parameter SizeReg = 10;
 
 reg [SRAMWordLength -1 :0] SRAM1 [0:SRAMSize -1];
 reg [SRAMWordLength -1 :0] SRAM2 [0:SRAMSize -1];
     
wire CLKA_ipd;
wire CLKB_ipd;

wire CSANeg_ipd;
wire CSBNeg_ipd;
wire ENA_ipd,ENB_ipd;

wire MBA_ipd,MBB_ipd;

 wire RTM_ipd, RFM_ipd;
                
 reg  ORBint,IRint;/////////////////////////??
wire RSTNeg_ipd,MRS2Neg_ipd,PRS2Neg_ipd,PRS1Neg_ipd,SIZE_ipd,SPMNeg_ipd,