idt723631.v

idt的双口ram的读写接口程序

        OutReg <= 0;
        MBF2Negint <= 1; pp_inp = 0;
        RETRMODE <=0;R3int<=0;CountR3int<=0;
        ChadowCountWords <=0;  ChadowOutReg <= 0;    //for RETRANSMIT MODE
        In1 =0; In3 =0;Wr =0; Rd =0;
        Viol1 =0; ReadNo = 1;
        X1 =0; Y1 =0;
       fork
        begin 
        repeat (4) @( posedge CLKA_ipd) if (RSTNeg_ipd) Viol1 =1 ;
                                                 // 4 CLKA clocks checking
        end
        begin
        repeat (4) @( posedge CLKB_ipd) if (RSTNeg_ipd) Viol1 =1 ;
                                           // 4 CLKB clocks checking
        end 
       begin
        repeat (3) @( posedge CLKB_ipd);
        ORBint <= 0; FWT1 <= 0;   FWT1S<= 0;ORBPint = 0;   //ORBint,FWT1 <= 0
        end     
       join
       if ( ! Viol1)
        begin
         WritePoint <= 0; ReadPoint <= 0; ChadowReadPoint <= 0;
         CountWords <= 0;  CountWords_P <= 0;
         @( posedge RSTNeg_ipd);
         repeat (2) @( posedge CLKA_ipd);
        end 
        else $display ("Time = %0d. FIFO1 Reset time is less 4 periods .\n ",
                        $time); 
      end
         
   always @( posedge RSTNeg_ipd)
                    // Loading FIFO1 AlFull-AlEmpty Offset regs X1,Y1
    
      case ( {FS1SEN_ipd,FS0SD_ipd})  
         
         2'b10:begin X1  = 64 ;Y1  = 64 ;end
         2'b01:begin X1  =  8; Y1  =  8; end
      endcase 
       
    reg  BigEndian, M_R;
    reg [8:0] Ser;    
     
    initial state =0;
     
    always                  // state mashine - implementation of  Reset  
      begin
        @( posedge CLKA_ipd);
        case (state)
         `IDLE :
           begin 
            if ( !RSTNeg_ipd ) state <= `MasterReset;
             M_R =0; 
           end
           
         `MasterReset:
           if (RSTNeg_ipd    )
            begin
              
              if ( !FS1SEN_ipd && !FS0SD_ipd )
                   state <= `ParProg; // Parallel programing
              
              else if ( FS1SEN_ipd&& FS0SD_ipd)
                   begin state <= `SerProg;Ser =1; Y1=0;X1=0;
                   end             // Serial programing
              else state <= `IDLE; // Preset values of Offset
             end
           
         `ParProg: if (!CSANeg_ipd && WRA_ipd && ENA_ipd && !MBA_ipd && IRint) 
                       begin Y1 = Ain[OffsetLength-1:0];
                       state <= `prX1; pp_inp = 1;
                       end

         `prX1:   if (!CSANeg_ipd && WRA_ipd && ENA_ipd && !MBA_ipd && IRint) 
                        begin X1 = Ain[OffsetLength-1:0];  
                        state <= `IDLE;
                        SRAM2_In1 <=1; Rd1 <=1;
                                    // start FFCIRCint  <= 1; with SKEW1
                        end 
                                  
         `SerProg:                                     // Serial programing
                   if(!FS1SEN_ipd)
                    begin
                     if( Ser <= NumBitProg/2)  Y1 = {Y1,FS0SD_ipd};
                     
                          else X1 = {X1,FS0SD_ipd};
                                
                    if( Ser == NumBitProg) begin 
                          In1 <=1; Rd <=1;      // start IRint  <= 1 with SKEW1 
                          @( posedge CLKB_ipd);
                          SRAM2_In1 <=1; Rd1 <=1;
                                     // start FFCIRCint  <= 1; with SKEW1
                          state <= `IDLE;
                         end     
                    else Ser <= Ser +1;  
                   end   
       endcase
     end 
     
     reg FIFO1_STD_Mode,FIFO2_STD_Mode;
                             
    ////////////////// port A operations /////////////////////////////////
   
     always @( Mail2 )        
               Mailout2 = Mail2;
               
    always @( CSANeg_ipd or WRA_ipd  or Mailout2 or MBA_ipd)
      if ( CSANeg_ipd | WRA_ipd ) Aout = 36 'h ZZZZZZZZZ; // no chip-select and no read from FIFO
      else  
        if (!CSANeg_ipd &&  !WRA_ipd )      //?? && MBA_ipd) 
                  
                   Aout = Mailout2;    //MAIL2 to bus A
                
    always @ (posedge En)
  // change by YAT for go En to 0 after 1 posedge CLKB  
     begin
     @(posedge CLKB_ipd );
     En <= @(negedge CLKB_ipd ) 0;
     end
                           
    always @( posedge CLKA_ipd )
     begin 
     
      case ( { CSANeg_ipd, WRA_ipd, ENA_ipd, MBA_ipd}) 
        4 'b0110: if (IRint &&( state == `IDLE) && RSTNeg_ipd) // write to FIFO
                   begin 
                    if (!RETRMODE )
                     begin
                        ORBPint <= 0;
                         // new change  YAT 06_11
                        if (( CountWords == 0) && FirstTime && ~ORBint &&
                              ~ren1 )  // ORB - my change YAT 
                                begin FWTTreg = Ain;
                                      FW =1;  //First writen word in FWTT mode
                                      FirstTime <=0;     // Assign to OutReg
                                      En  =1;
                                      if ( pp_inp == 1) pp_inp = 0;
  // include for pp_inp to 0 when we have first word
                           //         En <=@(negedge CLKB_ipd ) 0;

   // YAT 06/11/99 = end changing
                                end  
                        else 
                         begin
                     // end new change 
                     //////// FIFO1 write /////////
                          SRAM1 [WritePoint] <= Ain; FWT1S = 0; pp_inp =0;
                          if (WritePoint != (SRAMSize-1) )
                              WritePoint<= WritePoint +1;
                          else WritePoint <= 0;
                           CountWords_P = CountWords_P +1;
                           CountWords <=CountWords_P;
                         end
                      end             
                     else 
                      begin
                       ORBPint <= 0;
                       //////// FIFO1 write  in RETRANSMIT MODE write /////////
                       SRAM1 [WritePoint] <= Ain; FWT1S = 0;
                       if (WritePoint != (SRAMSize-1) )
                           WritePoint<= WritePoint +1;
                       else WritePoint <= 0;
                       ChadowCountWords <= ChadowCountWords +1;
                       CountWords_P = CountWords_P +1;
                       CountWords <=CountWords_P;
                      end 
                    end        
        4 'b0111: begin if (MBF1Negint) begin Mail1 = Ain ;
               MBF1Negint = 0; end end // Mail 1 Write 
        4 'b0011: begin  MBF2Negint = 1; Aout = Mailout2 ;
              end // Mail 2 Read / set MBF2
                     
       endcase 
     end 
    
  ////////////////////// port B operations /////////////////////////////////
             
       always @(  Mail1)     
              Mailout1 = Mail1;
                                 
  always @( CSBNeg_ipd or WRB_ipd or MBB_ipd  or Mailout1 or OutReg or ENB_ipd)
     begin 
       if ( CSBNeg_ipd || !WRB_ipd ) Bout = 36 'h ZZZZZZZZZ;
                               // no chip-select and no read from FIFO

       else if ( !CSBNeg_ipd && WRB_ipd  && ! MBB_ipd ) Bout = OutReg ;
            else  if ( !CSBNeg_ipd && WRB_ipd  && MBB_ipd ) Bout = Mailout1; 
     end
                          
 always @(posedge CLKB_ipd)
         begin 
          r1 <=FWTTreg;
          ren1 <=En;
          r2 <=r1; 
          ren2 <= ren1;                 
          if (ren2  )
           begin
            OutReg <= r2 ; 
           end
          
         end
  // YAT end pipeline 
                                      
//////////  set retransmit mode  flipflop RETRMODE  to 1 and Chadow registers
    always @( posedge CLKB_ipd ) 
           if (ORBint) 
              if (RTM_ipd && !RETRMODE)      begin 
                                  RETRMODE <= 1;
                                  ChadowReadPoint <=ReadPoint ;
                                            ChadowCountWords<=CountWords;
                                            ChadowOutReg<=OutReg;
                                             ChadowReadPoint_ptr = r1_ptr-1;
                                           // ChadowCountWords<= 0;
                                        end
    always
    begin
        @(ChadowCountWords)
             if (RSTNeg_ipd &&(ChadowCountWords < CountWords))
                ChadowCountWords<=CountWords;
    end

 //   DELAY  for 3 reading in the RETRMODE ,for check MIN 3  WORDS 
 //       (R3int <=  1 after 2  words reading)
 
    always  @( posedge CLKB_ipd ) 
   
    begin                       
       if( RETRMODE &&!CSBNeg_ipd && !MBB_ipd && WRB_ipd && ENB_ipd && ORBint )
               begin  if( CountR3int <= 4)  CountR3int<= CountR3int+1;
                  if( CountR3int == 2 ) R3int <=  1;
                end        
            end
    
   //    RETRMODE- start Retransmit from select position,
             always @( posedge CLKB_ipd )
                   if (  
                            RFM_ipd && RTM_ipd  && RETRMODE )
                     if( R3int)
                        begin
                                 ReadPoint   =   ChadowReadPoint;
                                 CountWords <= ChadowCountWords;
                                 CountWords_P <= ChadowCountWords;
                                 OutReg = ChadowOutReg;  // not delay ta !!
                                 CountR3int <=0;  R3int<=0;
                       end 
                       
                     else $display ("Time = %0d. FIFO retransmit loop
  less 3 words .\n ", $time);
                                 
   ////// RESET retransmit mode flipflop  RETRMODE

            always @( posedge CLKB_ipd )
             if (!RTM_ipd   )
                   begin  RETRMODE <=0;CountR3int <=0;  R3int<=0;end
 
     ///////  EMPTY / ALMOST EMPTY FLAGs behavior ///////////////////////

   always                                         ///// for FIFO1      
      begin
        @( CountWords);   
        if  ((CountWords == 0) && RSTNeg_ipd)
              begin    ORBPint <= 1;         // ORBint = 0;
                   FWT1 <= 0; //AENegint = 0;
                   FirstTime <= 1;
               end  
       end  
       
      // ORB fall delay  for tact   ////////////////////////////////////////
       
      always @( posedge CLKB_ipd ) 
     begin   
      case ( { CSBNeg_ipd, WRB_ipd, ENB_ipd, MBB_ipd ,RSTNeg_ipd}) 
        5'b01101:
          
            if (ORBPint) begin       //////// FIFO1 attempt Read //////////
                //    ORBint <= 0;
                    ORBPint <= 0;
                         end
     
      endcase
     end
     
  // ORB rise  ///////////////////////////////      
              
 always 
             begin   
               @( negedge WrFirstCell) ;
               repeat (2) @( posedge CLKB_ipd ) ;  // 3 to 2 !!!!!!!!!!!!!
              FWT1 <= 1;FWT1S <= 0;                // tREF after CLKB 
             end
             
    always 
   
             begin              //  FWT1 for Froufall First  World in FIFO1
             @( posedge FWT1 ) ;
             @( posedge CLKB_ipd ) ;
              FWT1S <= 0; FWT1 <= 0;        
            end
             
    always 
             begin   
               @( negedge WrAlEmCell) ;
               if (RSTNeg)begin
               repeat (2) @( posedge CLKB_ipd ) ; 
              end             // tREF after CLKB
             end
//----------------------
             
  // AE in the beginning of the RETRANSMIT LOOP //??           
             
       always 
       //  begin
          @( posedge CLKB_ipd )
              if (   RFM_ipd && RTM_ipd  && RETRMODE )
                  if (ChadowCountWords > (X1+1))
                             begin
                           repeat (2) @( posedge CLKB_ipd ) ; 
                        //   AENegint =  1;                                          
                              end
      //   end                     
      //----------------------- 

reg afla,  afla_old, af1l_a,  bcmpen_af_a,rcven_af_a, af2la_a;
reg  aflgen_a,no_inc_w1;
reg ira,orb, ORB1int;
reg [SizeReg:0] wtp_1,wtp_2, afp_a, r1_ptr_retr;
wire  mrstl1,prstl1,csal,ena,wrla,mba; 
wire [SizeReg - 1:0] y1;
 
assign  mrstl1 = RSTNeg_ipd;
assign prstl1 =1'b1; 
assign csal = CSANeg_ipd;
assign ena = ENA_ipd;
assign wrla = WRA_ipd;
assign mba = MBA_ipd;
assign y1 = Y1;
assign AFNegint = afla;
reg ira_in,irb_in,ira_old,ff1l_a,fflgen_a;
reg irhdl1_lchd_a;
reg ff1l_b,fflgen_b;
reg irhdl1_lchd_b;
reg fs0_reg,fs1_reg,spml,pp_end,sp_end,palcntl,sercntl,irhdl2,irhdl1;
reg  aflgen_b,en_irb,en2_irb, counter1_irb ,counter2_irb,eql_orb;
wire fs0sd,fs1senl,befwftl;
assign fs0sd = FS0SD_ipd;
assign  fs1senl=FS1SEN_ipd;
assign befwftl = 1'b0;
reg   rcven_ae_a_old,  bcmpen_ae_a, rcven_ae_a;
reg ora_old,ef2l_a_old;
wire  unienl;     
reg  aelgen_a,eflgen_a;
reg [SizeReg:0]  aep_a;