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来自「综合仿真程序」· Verilog 代码 · 共 11 行

module Shift(CLK,DIN,DOUT);
     input CLK;
     input DIN;
     output [3:0] DOUT;
     reg [3:0] DOUT; 
always @(posedge CLK) 
begin
   DOUT  <= {DIN, DOUT[3:1]};
end
endmodule