top.v

综合仿真程序

module Shift(CLK,DIN,DOUT);
     input CLK;
     input DIN;
     output [3:0] DOUT;
     reg [3:0] DOUT; 
always @(posedge CLK) 
begin
   DOUT  <= {DIN, DOUT[3:1]};
end
endmodule