_primary.vhd

来自「综合仿真程序」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity d_flip_flop is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        din             : in     vl_logic;
        dout            : out    vl_logic
    );
end d_flip_flop;