_primary.vhd

来自「综合仿真程序」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity ex1 is
    port(
        a               : in     vl_logic;
        b               : in     vl_logic;
        c               : in     vl_logic;
        d               : in     vl_logic;
        e               : out    vl_logic
    );
end ex1;