ca-vfdl.txt

GPS C/A码 发生器 LFSR 源代码 VHDL 语言

library ieee;
use ieee.std_logic_1164.all;
entity LFSR_A is
generic(cycleA0:integer:=26;
        cycleA3:integer:=4;
        width:integer:=1);
 port(Clk:in std_logic;
      Enable:in std_logic;
      Fill_En:in std_logic;
      New_Fill:in std_logic_vector(width -1 downto 0);
      DelayA0;out std_logic_vector(width -1 downto 0));
end LFSR_A;
architecture LFSR_A_ARCH of LFSR_A is
signal Date_In_A:STD_LOGIC_VECTOR(width -1 downto 0);
signal DelayA3:STD_LOGIC_VECTOR(width -1 downto 0);
signal DelayA0_int:STD_LOGIC_VECTOR(width -1 downto 0);

type my_type is array(0 to cycleA0 -1) of
std_logic_vector(width -1 downto 0);
signal int_sigA0:my_type;
type my_type2 is array (0 to cycleA3 -1) of
std_logic_vector(width -1 downto 0);
signal int_sigA3:my_type2;

begin
main:process(Clk)
begin
if Clk event and Clk ='1' then
 if (Enable='1') then
  int_sigA0<=Data_In_A & int_sigA0(0 to cycleA0 -2);
   int_sigA3<=Data_In_A & int_sigA3(0 to cycleA3 -2);
 end if;
 if (Fill_En='0') then Data_In_A<=DelayA3 xor DelayA0_int;
 else Data_In_A<=New_Fill;
 end if;
end if;
end process main;

delayA0_int<=int_sigA0(cycleA0 -1);
delayA3<=int_sigA3(cycleA3 -1);
delayA0<=delayA0_int;
end LFSR_A_ARCH;

library ieee;
use ieee.std_logic_1164.all;
entity LFSR_B is
generic (cycleB0:integer:=26;
cycleB20:integer:=21;
width:integer:=1);
 port(Clk:in std_logic;
      Enable:in std_logic;
      Fill_En:in std_logic;
      New_Fill:in std_logic_vector(width -1 downto 0);
      DelayB0:out std_logic_vector(width -1 downto 0));
end LFSR_B;

architecture LFSR_B_ARCH of LFSR_B is
signal Data_In_B:std_logic_vector(width -1 downto 0);
signal DelayB20:std_logic_vector(width -1 downto 0);
signal DelayB0_int:std_logic_vector(width -1 downto 0);
type my_type is array (0 to cycleB0 -1) of
std_logic_vector(width -1 downto 0);
signal int_sigB0:my_type;
type my_type2 is array(0 to cycleB20 -1) of
std_logic_vector(width -1 downto 0);
signal int_sigB20:my_type2;

begin
main:process(Clk)
begin
if Clk event and Clk='1' then
 if (Enable='1') then
  int_sigB0<=Data_In_B & int_sigB0(0 to cycleB0 -2);
  int_sigB20<=Data_In_B & int_sigB20(0 to cycleB20 -2);
 end if;
 if (Fill_En='0') then Data_In_B<=DelayB20 xor DelayB0_int;
 else Data_In_B<=New_Fill;
 end if:
end if;
end process main;

delayB0_int<=int_sigB0(cycleB0 -1);
delayB20<=int_sigB20(cycleB20 -1);
delayB0<=delayB0_int;
end LFSR_B_ARCH;

library ieee;
use ieee.std_logic_1164.all;
entity Gold_Code is
generic (width:integer:=1);
 port(Clock:in std_logic;
      Enable:in std_logic;
      Fill_En_A:in std_logic;
      Fill_En_B:in std_logic;
      Rst:in std_logic;
      New_Fill_A:in std_logic_vector(width -1 downto 0);
      New_Fill_B:in std_logic_vector(width -1 downto 0);
      Gold_Code:out std_logic_vector(width -1 downto 0));
end Gold_Code;

architecture Gold_Code_Arch of Gold_Code is
component LFSR_A port
 (Clk:in std_logic;
  Enable:in std_logic;
  Fill_En:in std_logic;
  New_Fill:in std_logic_vector(width -1 downto 0);
  delayA0:out std_logic_vector(width -1 downto 0));
end component;
component LFSR_B port
 (Clk:in std_logic;
  Enable:in std_logic;
  Fill_En:in std_logic;
  New_Fill:in std_logic_vector(width -1 downto 0);
  delayB0:out std_logic_vector(width -1 downto 0));
end component;

signal DelayA_top:std_logic_vector(width -1 downto 0);
signal DelayB_top:std_logic_vector(width -1 downto 0);

begin
U0:LFSR_A port map (Clk=>Clock,Enable=>Enable,
                    Fill_En=>Fill_En_A,
                    New_Fill=>New_Fill_A,
                    delayA0=>delayA_top);
U1:LFSR_B port map (Clk=>Clock,Enable=>Enable,
                    Fill_En=>Fill_En_B,
                    New_Fill=>New_Fill_B,
                    delayB0=>delayB_top);
Gold_Code<=delayB xor delayA_top;
end Gold_Code_Arch;