full_featured.fit.rpt

来自「一个毕业设计」· RPT 代码 · 共 392 行 · 第 1/5 页

Fitter report for full_featured
Tue Apr 27 23:40:53 2004
Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Register Duplication into IO's
  6. Fitter Equations
  7. Floorplan View
  8. Pin-Out File
  9. Fitter Resource Usage Summary
 10. Input Pins
 11. Output Pins
 12. Bidir Pins
 13. I/O Bank Usage
 14. All Package Pins
 15. PLL Summary
 16. PLL Usage
 17. Output Pin Load For Reported TCO
 18. Fitter Resource Utilization by Entity
 19. Delay Chain Summary
 20. Pad To Core Delay Chain Fanout
 21. Control Signals
 22. Global & Other Fast Signals
 23. Non-Global High Fan-Out Signals
 24. Fitter RAM Summary
 25. Interconnect Usage Summary
 26. LAB Logic Elements
 27. LAB-wide Signals
 28. LAB Signals Sourced
 29. LAB Signals Sourced Out
 30. LAB Distinct Inputs
 31. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+---------------------------------------------------------------+
; Fitter Summary                                                ;
+-----------------------+---------------------------------------+
; Fitter Status         ; Successful - Tue Apr 27 23:40:53 2004 ;
; Revision Name         ; full_featured                         ;
; Top-level Entity Name ; full_featured                         ;
; Family                ; Cyclone                               ;
; Device                ; EP1C20F400C7                          ;
; Total logic elements  ; 8,449 / 20,060 ( 42 % )               ;
; Total pins            ; 196 / 301 ( 65 % )                    ;
; Total memory bits     ; 84,608 / 294,912 ( 28 % )             ;
; Total PLLs            ; 2 / 2 ( 100 % )                       ;