full_featured.fit.rpt

来自「一个毕业设计」· RPT 代码 · 共 392 行 · 第 1/5 页

+-----------------------+---------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                                                              ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Option                                                                                                     ; Setting                        ; Default Value                  ;
+------------------------------------------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                                                     ; EP1C20F400C7                   ;                                ;
; Auto Register Duplication                                                                                  ; Off                            ; Off                            ;
; Logic Cell Insertion -- Logic Duplication                                                                  ; Auto                           ; Auto                           ;
; Perform physical synthesis with extra effort; uses extra compile time to try for extra circuit performance ; Off                            ; Off                            ;
; Perform Register Retiming                                                                                  ; Off                            ; Off                            ;
; Perform Register Duplication                                                                               ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic                                                         ; Off                            ; Off                            ;
; Auto Merge PLLs                                                                                            ; On                             ; On                             ;
; Auto Delay Chains                                                                                          ; On                             ; On                             ;
; Auto Packed Registers -- Cyclone                                                                           ; Normal                         ; Normal                         ;
; Auto Global Memory Control Signals                                                                         ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                                                                  ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                                                      ; Off                            ; Off                            ;
; PCI I/O                                                                                                    ; Off                            ; Off                            ;
; Slow Slew Rate                                                                                             ; Off                            ; Off                            ;
; Fitter Initial Placement Seed                                                                              ; 1                              ; 1                              ;
; Final Placement Optimizations                                                                              ; Automatically                  ; Automatically                  ;
; FIT_ONLY_ONE_ATTEMPT                                                                                       ; Off                            ; Off                            ;
; Optimize IOC Register Placement for Timing                                                                 ; On                             ; On                             ;
; Optimize Timing                                                                                            ; Normal Compilation             ; Normal Compilation             ;
; Optimize Hold Timing                                                                                       ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+------------------------------------------------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+---------------------------------------------------------------------
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Auto-restart configuration after error       ; On                  ;
; Release clears before tri-states             ; Off                 ;
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+--------------------------------+
; Register Duplication into IO's ;
+---------------------------------
; Atom Name    ; State           ;
+--------------+-----------------+
; SDRAM_A[5]   ; Modified        ;
; SDRAM_A[7]   ; Modified        ;
; SDRAM_BA[0]  ; Modified        ;
; SDRAM_BA[1]  ; Modified        ;
; SDRAM_CAS_N  ; Modified        ;
; SDRAM_DQM[0] ; Modified        ;
; SDRAM_DQM[1] ; Modified        ;
; SDRAM_DQM[2] ; Modified        ;
; SDRAM_DQM[3] ; Modified        ;
; SDRAM_DQ[0]  ; Modified        ;
; SDRAM_DQ[10] ; Modified        ;
; SDRAM_DQ[11] ; Modified        ;
; SDRAM_DQ[12] ; Modified        ;
; SDRAM_DQ[13] ; Modified        ;
; SDRAM_DQ[14] ; Modified        ;
; SDRAM_DQ[15] ; Modified        ;
; SDRAM_DQ[16] ; Modified        ;
; SDRAM_DQ[17] ; Modified        ;
; SDRAM_DQ[18] ; Modified        ;
; SDRAM_DQ[19] ; Modified        ;
; SDRAM_DQ[1]  ; Modified        ;
; SDRAM_DQ[20] ; Modified        ;
; SDRAM_DQ[21] ; Modified        ;
; SDRAM_DQ[22] ; Modified        ;
; SDRAM_DQ[23] ; Modified        ;
; SDRAM_DQ[24] ; Modified        ;