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📄 top.rpt

📁 一个用VHDL编写的在CPLD上实现模拟交通灯的程序源代码
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   -      8     -    C    10        OR2    s           0    4    0    1  |TRAFFIC_CON:4|~1348~4
   -      8     -    C    05        OR2    s           0    3    0    6  |TRAFFIC_CON:4|~1350~1
   -      4     -    C    19        OR2    s           0    3    0    1  |TRAFFIC_CON:4|~1361~1
   -      2     -    C    06       AND2                1    0    0    1  |TRAFFIC_CON:4|:1436
   -      1     -    C    08        OR2                1    0    0    1  |TRAFFIC_CON:4|:1445
   -      4     -    C    11       AND2                1    0    0    1  |TRAFFIC_CON:4|:1454
   -      2     -    C    20        OR2                1    0    0    1  |TRAFFIC_CON:4|:1463
   -      1     -    C    22       AND2                1    0    0    1  |TRAFFIC_CON:4|:1472
   -      2     -    C    15        OR2                1    0    0    1  |TRAFFIC_CON:4|:1481
   -      3     -    C    12       AND2                1    0    0    1  |TRAFFIC_CON:4|:1490
   -      4     -    C    10        OR2                1    0    0    1  |TRAFFIC_CON:4|:1499
   -      2     -    C    05       AND2                1    0    0    1  |TRAFFIC_CON:4|:1508
   -      5     -    C    05       AND2                1    0    0    1  |TRAFFIC_CON:4|:1517
   -      2     -    C    11       AND2                1    0    0    1  |TRAFFIC_CON:4|:1526
   -      2     -    C    04        OR2                1    0    0    1  |TRAFFIC_CON:4|:1535
   -      2     -    C    13       AND2                1    0    0    1  |TRAFFIC_CON:4|:1544
   -      2     -    C    07       AND2                1    0    0    1  |TRAFFIC_CON:4|:1553
   -      1     -    C    12       AND2                1    0    0    1  |TRAFFIC_CON:4|:1562
   -      3     -    C    10       AND2                1    0    0    1  |TRAFFIC_CON:4|:1571
   -      1     -    C    02       AND2                1    0    0    1  |TRAFFIC_CON:4|:1580
   -      1     -    C    03       AND2                1    0    0    1  |TRAFFIC_CON:4|:1589
   -      3     -    C    11        OR2                1    0    0    1  |TRAFFIC_CON:4|:1598
   -      3     -    C    04        OR2                1    0    0    1  |TRAFFIC_CON:4|:1607
   -      2     -    C    24       AND2                1    0    0    1  |TRAFFIC_CON:4|:1616
   -      3     -    C    07       AND2                1    0    0    1  |TRAFFIC_CON:4|:1625
   -      2     -    C    23       AND2                1    0    0    1  |TRAFFIC_CON:4|:1634
   -      2     -    C    10       AND2                1    0    0    1  |TRAFFIC_CON:4|:1643
   -      8     -    B    06       DFFE   +            0    3    0   16  |TRAFFIC_CON:4|tempb (|TRAFFIC_CON:4|:1701)
   -      4     -    C    21       AND2                0    3    0    8  |TRAFFIC_CON:4|:2062
   -      3     -    B    13        OR2                0    3    0    1  |TRAFFIC_CON:4|:2065
   -      1     -    C    21        OR2        !       0    3    0    8  |TRAFFIC_CON:4|:2072
   -      4     -    B    13        OR2                0    3    0    1  |TRAFFIC_CON:4|:2075
   -      3     -    C    21       AND2                0    3    0    8  |TRAFFIC_CON:4|:2082
   -      5     -    B    13        OR2                0    3    0    1  |TRAFFIC_CON:4|:2085
   -      1     -    C    14       AND2                0    3    0   11  |TRAFFIC_CON:4|:2092
   -      6     -    B    13        OR2                0    3    0    1  |TRAFFIC_CON:4|:2095
   -      2     -    B    21        OR2                0    3    0    1  |TRAFFIC_CON:4|:2104
   -      3     -    B    21        OR2                0    3    0    1  |TRAFFIC_CON:4|:2107
   -      4     -    B    21        OR2                0    3    0    1  |TRAFFIC_CON:4|:2110
   -      5     -    B    21        OR2                0    3    0    1  |TRAFFIC_CON:4|:2113
   -      5     -    B    02        OR2                0    3    0    1  |TRAFFIC_CON:4|:2122
   -      6     -    B    02        OR2                0    3    0    1  |TRAFFIC_CON:4|:2125
   -      7     -    B    02        OR2                0    3    0    1  |TRAFFIC_CON:4|:2128
   -      8     -    B    02        OR2                0    3    0    1  |TRAFFIC_CON:4|:2131
   -      5     -    B    14        OR2                0    3    0    1  |TRAFFIC_CON:4|:2140
   -      6     -    B    14        OR2                0    3    0    1  |TRAFFIC_CON:4|:2143
   -      7     -    B    14        OR2                0    3    0    1  |TRAFFIC_CON:4|:2146
   -      4     -    B    05        OR2                0    3    0    1  |TRAFFIC_CON:4|:2158
   -      5     -    B    05        OR2                0    3    0    1  |TRAFFIC_CON:4|:2161
   -      6     -    B    05        OR2                0    3    0    1  |TRAFFIC_CON:4|:2164
   -      5     -    B    01        OR2                0    3    0    1  |TRAFFIC_CON:4|:2176
   -      6     -    B    01        OR2                0    3    0    1  |TRAFFIC_CON:4|:2179
   -      7     -    B    01        OR2                0    3    0    1  |TRAFFIC_CON:4|:2182
   -      5     -    B    08        OR2                0    3    0    1  |TRAFFIC_CON:4|:2194
   -      6     -    B    08        OR2                0    3    0    1  |TRAFFIC_CON:4|:2197
   -      7     -    B    08        OR2                0    3    0    1  |TRAFFIC_CON:4|:2200
   -      5     -    B    07        OR2                0    3    0    1  |TRAFFIC_CON:4|:2212
   -      6     -    B    07        OR2                0    3    0    1  |TRAFFIC_CON:4|:2215
   -      7     -    B    07        OR2                0    3    0    1  |TRAFFIC_CON:4|:2218
   -      8     -    B    07        OR2                0    3    0    1  |TRAFFIC_CON:4|:2221
   -      8     -    C    21        OR2        !       0    4    0    1  |TRAFFIC_CON:4|:2241
   -      2     -    C    14        OR2                0    4    0    1  |TRAFFIC_CON:4|:2272
   -      2     -    B    06        OR2        !       0    2    0    6  |TRAFFIC_CON:4|:2398
   -      1     -    B    21        OR2        !       0    4    0    5  |TRAFFIC_CON:4|:2546
   -      8     -    B    13        OR2                0    4    0    1  |TRAFFIC_CON:4|:2774
   -      7     -    B    21        OR2                0    4    0    1  |TRAFFIC_CON:4|:2780
   -      3     -    B    06        OR2                0    4    0    1  |TRAFFIC_CON:4|:2786
   -      8     -    B    14        OR2                0    4    0    1  |TRAFFIC_CON:4|:2923
   -      7     -    B    05        OR2                0    4    0    1  |TRAFFIC_CON:4|:2929
   -      8     -    B    01        OR2                0    4    0    1  |TRAFFIC_CON:4|:2935
   -      8     -    B    08        OR2                0    4    0    1  |TRAFFIC_CON:4|:2941
   -      6     -    B    06       AND2    s           0    2    0    2  |TRAFFIC_CON:4|~2942~1
   -      4     -    B    06        OR2    s           0    3    0    6  |TRAFFIC_CON:4|~2948~1
   -      3     -    C    14        OR2    s           0    4    0    1  |TRAFFIC_CON:4|~2959~1
   -      2     -    B    18       AND2                1    0    0    1  |TRAFFIC_CON:4|:3034
   -      1     -    B    19        OR2                1    0    0    1  |TRAFFIC_CON:4|:3043
   -      1     -    B    02       AND2                1    0    0    1  |TRAFFIC_CON:4|:3052
   -      2     -    B    14       AND2                1    0    0    1  |TRAFFIC_CON:4|:3061
   -      1     -    B    05       AND2                1    0    0    1  |TRAFFIC_CON:4|:3070
   -      1     -    B    01       AND2                1    0    0    1  |TRAFFIC_CON:4|:3079
   -      2     -    B    08       AND2                1    0    0    1  |TRAFFIC_CON:4|:3088
   -      2     -    B    07       AND2                1    0    0    1  |TRAFFIC_CON:4|:3097
   -      2     -    B    13       AND2                1    0    0    1  |TRAFFIC_CON:4|:3106
   -      1     -    B    16        OR2                1    0    0    1  |TRAFFIC_CON:4|:3115
   -      4     -    B    02       AND2                1    0    0    1  |TRAFFIC_CON:4|:3124
   -      4     -    B    14        OR2                1    0    0    1  |TRAFFIC_CON:4|:3133
   -      3     -    B    05       AND2                1    0    0    1  |TRAFFIC_CON:4|:3142
   -      4     -    B    01       AND2                1    0    0    1  |TRAFFIC_CON:4|:3151
   -      4     -    B    08       AND2                1    0    0    1  |TRAFFIC_CON:4|:3160
   -      4     -    B    07       AND2                1    0    0    1  |TRAFFIC_CON:4|:3169
   -      1     -    B    22       AND2                1    0    0    1  |TRAFFIC_CON:4|:3178
   -      1     -    B    24       AND2                1    0    0    1  |TRAFFIC_CON:4|:3187
   -      3     -    B    02       AND2                1    0    0    1  |TRAFFIC_CON:4|:3196
   -      3     -    B    14       AND2                1    0    0    1  |TRAFFIC_CON:4|:3205
   -      2     -    B    05       AND2                1    0    0    1  |TRAFFIC_CON:4|:3214
   -      3     -    B    01        OR2                1    0    0    1  |TRAFFIC_CON:4|:3223
   -      3     -    B    08       AND2                1    0    0    1  |TRAFFIC_CON:4|:3232
   -      3     -    B    07        OR2                1    0    0    1  |TRAFFIC_CON:4|:3241


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register


Device-Specific Information:                 d:\work\vhdl\jiaotongdeng\top.rpt
top

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       3/ 96(  3%)     4/ 48(  8%)     0/ 48(  0%)    0/16(  0%)      7/16( 43%)     0/16(  0%)
B:      24/ 96( 25%)    19/ 48( 39%)     8/ 48( 16%)    0/16(  0%)      6/16( 37%)     0/16(  0%)
C:      36/ 96( 37%)     1/ 48(  2%)     5/ 48( 10%)    0/16(  0%)      3/16( 18%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      5/24( 20%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      2/24(  8%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      3/24( 12%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                 d:\work\vhdl\jiaotongdeng\top.rpt
top

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       30         clk
INPUT        3         clk_scan


Device-Specific Information:                 d:\work\vhdl\jiaotongdeng\top.rpt
top

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT       78         reset


Device-Specific Information:                 d:\work\vhdl\jiaotongdeng\top.rpt
top

** EQUATIONS **

clk      : INPUT;
clk_scan : INPUT;
reset    : INPUT;

-- Node name is 'a' 
-- Equation name is 'a', type is output 
a        =  _LC4_B10;

-- Node name is 'b' 
-- Equation name is 'b', type is output 
b        =  _LC2_B10;

-- Node name is 'c' 
-- Equation name is 'c', type is output 
c        =  _LC8_B10;

-- Node name is 'd' 
-- Equation name is 'd', type is output 
d        =  _LC7_B12;

-- Node name is 'e' 
-- Equation name is 'e', type is output 
e        =  _LC1_B12;

-- Node name is 'f' 
-- Equation name is 'f', type is output 
f        =  _LC1_B10;

-- Node name is 'g' 
-- Equation name is 'g', type is output 
g        =  _LC4_B11;

-- Node name is 'lampa0' 
-- Equation name is 'lampa0', type is output 
lampa0   =  _LC7_C19;

-- Node name is 'lampa1' 
-- Equation name is 'lampa1', type is output 
lampa1   =  _LC5_C19;

-- Node name is 'lampa2' 
-- Equation name is 'lampa2', type is output 
lampa2   =  _LC3_C19;

-- Node name is 'lampb0' 
-- Equation name is 'lampb0', type is output 
lampb0   =  _LC5_C14;

-- Node name is 'lampb1' 
-- Equation name is 'lampb1', type is output 
lampb1   =  _LC4_C14;

-- Node name is 'lampb2' 
-- Equation name is 'lampb2', type is output 
lampb2   =  _LC2_C21;

-- Node name is 'sel0' 
-- Equation name is 'sel0', type is output 
sel0     =  _LC3_B9;

-- Node name is 'sel1' 
-- Equation name is 'sel1', type is output 
sel1     =  _LC2_B9;

-- Node name is 'sel2' 
-- Equation name is 'sel2', type is output 
sel2     =  _LC1_B9;

-- Node name is '|DECODER:1|:432' 
-- Equation name is '_LC5_B10', type is buried 
_LC5_B10 = LCELL( _EQ001);
  _EQ001 = !_LC1_B3 & !_LC3_B11 &  _LC5_B3 &  _LC5_B11;

-- Node name is '|DECODER:1|:444' 
-- Equation name is '_LC3_B10', type is buried 

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