📄 decoder.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port(din : in std_logic_vector(3 downto 0);
a,b,c,d,e,f,g :out std_logic
);
end decoder;
architecture behave of decoder is
signal decod_out :std_logic_vector(6 downto 0);
begin
process(din)
begin
case din is
when "0000" => decod_out<="1111110";
when "0001" => decod_out<="0110000";
when "0010" => decod_out<="1101101";
when "0011" => decod_out<="1111001";
when "0100" => decod_out<="0110011";
when "0101" => decod_out<="1011011";
when "0110" => decod_out<="1011111";
when "0111" => decod_out<="1110000";
when "1000" => decod_out<="1111111";
when "1001" => decod_out<="1111011";
when "1010" => decod_out<="1110111";
when "1011" => decod_out<="0011111";
when "1100" => decod_out<="1001110";
when "1101" => decod_out<="0111101";
when "1110" => decod_out<="1001111";
when "1111" => decod_out<="1000111";
when others => null;
end case;
end process;
a<=decod_out(6);
b<=decod_out(5);
c<=decod_out(4);
d<=decod_out(3);
e<=decod_out(2);
f<=decod_out(1);
g<=decod_out(0);
end behave;
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