📄 mux4.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux4 is
port(ina,inb : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0);
dout : out std_logic_vector(3 downto 0)
);
end mux4;
architecture behave of mux4 is
begin
process(ina,inb,sel)
begin
case sel is
when "000" => dout<=ina(7 downto 4);
when "001" => dout<=ina(3 downto 0);
when "110" => dout<=inb(7 downto 4);
when "111" => dout<=inb(3 downto 0);
when others => null;
end case;
end process;
end behave;
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