📄 decoder.rpt
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Device-Specific Information: d:\work\vhdl\jiaotongdeng\decoder.rpt
decoder
** EQUATIONS **
din0 : INPUT;
din1 : INPUT;
din2 : INPUT;
din3 : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC4_B1;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC1_B3;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC8_B20;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC1_B20;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC2_B20;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC8_B3;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC6_B1;
-- Node name is '~444~1'
-- Equation name is '~444~1', location is LC2_B3, type is buried.
-- synthesized logic cell
_LC2_B3 = LCELL( _EQ001);
_EQ001 = !din2 & din3;
-- Node name is ':456'
-- Equation name is '_LC8_B1', type is buried
!_LC8_B1 = _LC8_B1~NOT;
_LC8_B1~NOT = LCELL( _EQ002);
_EQ002 = !din1
# !din0
# din3
# !din2;
-- Node name is ':492'
-- Equation name is '_LC3_B1', type is buried
!_LC3_B1 = _LC3_B1~NOT;
_LC3_B1~NOT = LCELL( _EQ003);
_EQ003 = din1
# din0
# din3
# !din2;
-- Node name is ':528'
-- Equation name is '_LC5_B20', type is buried
!_LC5_B20 = _LC5_B20~NOT;
_LC5_B20~NOT = LCELL( _EQ004);
_EQ004 = din1
# !din0
# din3
# din2;
-- Node name is ':540'
-- Equation name is '_LC3_B20', type is buried
_LC3_B20 = LCELL( _EQ005);
_EQ005 = !din0 & !din1 & !din2 & !din3;
-- Node name is ':543'
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = LCELL( _EQ006);
_EQ006 = din1 & din2
# !din0 & din1
# din1 & !din3
# !din0 & din3
# !din0 & !din2
# !din1 & !din2 & din3
# din0 & din2 & !din3;
-- Node name is ':591'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ007);
_EQ007 = din0 & !din1 & din3
# !din1 & !din2
# !din0 & !din1 & !din3
# !din0 & !din2
# din0 & din1 & !din3;
-- Node name is ':638'
-- Equation name is '_LC7_B20', type is buried
_LC7_B20 = LCELL( _EQ008);
_EQ008 = !din2 & din3
# din0 & !din1 & din3
# din2 & !din3
# din0 & din1 & !din3;
-- Node name is ':639'
-- Equation name is '_LC8_B20', type is buried
_LC8_B20 = LCELL( _EQ009);
_EQ009 = _LC3_B20
# _LC5_B20
# _LC7_B20;
-- Node name is '~687~1'
-- Equation name is '~687~1', location is LC5_B1, type is buried.
-- synthesized logic cell
_LC5_B1 = LCELL( _EQ010);
_EQ010 = din0 & din1 & !din2 & din3
# !din0 & din2 & din3
# !din1 & din2 & din3;
-- Node name is '~687~2'
-- Equation name is '~687~2', location is LC7_B1, type is buried.
-- synthesized logic cell
_LC7_B1 = LCELL( _EQ011);
_EQ011 = !din1 & _LC2_B3
# _LC5_B1;
-- Node name is '~687~3'
-- Equation name is '~687~3', location is LC1_B1, type is buried.
-- synthesized logic cell
_LC1_B1 = LCELL( _EQ012);
_EQ012 = _LC2_B1 & !_LC3_B1
# !_LC3_B1 & _LC7_B1 & !_LC8_B1;
-- Node name is ':687'
-- Equation name is '_LC1_B20', type is buried
_LC1_B20 = LCELL( _EQ013);
_EQ013 = !_LC5_B20 & _LC6_B20
# _LC1_B1 & !_LC5_B20
# _LC3_B20;
-- Node name is ':729'
-- Equation name is '_LC4_B20', type is buried
_LC4_B20 = LCELL( _EQ014);
_EQ014 = !din0 & din1
# !din0 & !din2
# din2 & din3
# din1 & din3
# !din0 & din3
# !din1 & !din2 & !din3;
-- Node name is ':735'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = LCELL( _EQ015);
_EQ015 = _LC3_B20
# _LC4_B20 & !_LC5_B20;
-- Node name is '~771~1'
-- Equation name is '~771~1', location is LC2_B1, type is buried.
-- synthesized logic cell
_LC2_B1 = LCELL( _EQ016);
_EQ016 = din0 & !din1 & din2 & !din3
# !din0 & din1 & din2 & !din3;
-- Node name is ':783'
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = LCELL( _EQ017);
_EQ017 = din1 & din3
# !din0 & !din1
# !din0 & din2
# !din0 & din3
# !din2 & din3
# !din1 & din2 & !din3;
-- Node name is '~825~1'
-- Equation name is '~825~1', location is LC6_B20, type is buried.
-- synthesized logic cell
_LC6_B20 = LCELL( _EQ018);
_EQ018 = din1 & !din2 & !din3;
-- Node name is ':833'
-- Equation name is '_LC6_B1', type is buried
_LC6_B1 = LCELL( _EQ019);
_EQ019 = !din0 & din1
# din1 & din3
# din0 & din3
# din1 & !din2
# !din2 & din3
# din0 & !din1 & din2
# !din1 & din2 & !din3
# !din0 & din2 & !din3;
Project Information d:\work\vhdl\jiaotongdeng\decoder.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,278K
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