📄 traffic_con.rpt
字号:
71 - - A -- OUTPUT 0 1 0 0 leda3
6 - - A -- OUTPUT 0 1 0 0 leda4
9 - - A -- OUTPUT 0 1 0 0 leda5
8 - - A -- OUTPUT 0 1 0 0 leda6
5 - - A -- OUTPUT 0 1 0 0 leda7
16 - - B -- OUTPUT 0 1 0 0 ledb0
14 - - B -- OUTPUT 0 1 0 0 ledb1
13 - - B -- OUTPUT 0 1 0 0 ledb2
15 - - B -- OUTPUT 0 1 0 0 ledb3
62 - - B -- OUTPUT 0 1 0 0 ledb4
64 - - B -- OUTPUT 0 1 0 0 ledb5
65 - - B -- OUTPUT 0 1 0 0 ledb6
46 - - - 10 OUTPUT 0 1 0 0 ledb7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\work\vhdl\jiaotongdeng\traffic_con.rpt
traffic_con
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 22 OR2 0 2 0 3 |LPM_ADD_SUB:1002|addcore:adder|pcarry1
- 8 - A 05 OR2 0 2 0 3 |LPM_ADD_SUB:1130|addcore:adder|pcarry1
- 2 - B 06 OR2 0 2 0 3 |LPM_ADD_SUB:2600|addcore:adder|pcarry1
- 2 - B 15 OR2 0 2 0 3 |LPM_ADD_SUB:2728|addcore:adder|pcarry1
- 1 - A 14 DFFE + ! 0 3 1 0 :3
- 8 - A 14 DFFE + 0 3 1 1 :5
- 2 - A 14 DFFE + 0 3 1 1 :7
- 8 - B 03 DFFE + ! 0 3 1 1 :9
- 4 - B 03 DFFE + 0 3 1 1 :11
- 6 - B 03 DFFE + 0 3 1 1 :13
- 4 - A 14 DFFE + 0 3 0 8 statea2 (:31)
- 1 - A 18 DFFE + 0 3 0 6 statea1 (:32)
- 2 - A 18 DFFE + 0 3 0 6 statea0 (:33)
- 1 - A 20 DFFE + 0 4 1 5 counta7 (:34)
- 8 - A 22 DFFE + 0 4 1 6 counta6 (:35)
- 7 - A 23 DFFE + 0 4 1 5 counta5 (:36)
- 2 - A 16 DFFE + 0 3 1 5 counta4 (:37)
- 1 - A 12 DFFE + 0 4 1 5 counta3 (:38)
- 8 - A 04 DFFE + 0 3 1 5 counta2 (:39)
- 2 - A 02 DFFE + 0 3 1 4 counta1 (:40)
- 7 - A 11 DFFE + 0 3 1 3 counta0 (:41)
- 7 - B 05 DFFE + 0 3 0 9 stateb2 (:66)
- 4 - B 05 DFFE + 0 3 0 9 stateb1 (:67)
- 3 - B 05 DFFE + 0 3 0 9 stateb0 (:68)
- 1 - B 10 DFFE + 0 4 1 4 countb7 (:69)
- 1 - B 02 DFFE + 0 4 1 5 countb6 (:70)
- 2 - B 09 DFFE + 0 4 1 4 countb5 (:71)
- 5 - B 08 DFFE + 0 3 1 4 countb4 (:72)
- 5 - B 23 DFFE + 0 4 1 4 countb3 (:73)
- 1 - B 16 DFFE + 0 3 1 4 countb2 (:74)
- 3 - B 17 DFFE + 0 3 1 3 countb1 (:75)
- 7 - B 14 DFFE + 0 3 1 4 countb0 (:76)
- 7 - A 14 OR2 s ! 0 2 0 1 tempa~1 (~103~1)
- 5 - A 22 DFFE + 0 2 0 16 tempa (:103)
- 3 - A 18 OR2 ! 0 3 0 13 :454
- 4 - A 20 OR2 0 3 0 1 :457
- 4 - A 18 AND2 0 3 0 13 :464
- 5 - A 20 OR2 0 3 0 1 :467
- 6 - A 18 OR2 ! 0 3 0 10 :474
- 6 - A 20 OR2 0 3 0 1 :477
- 5 - A 18 OR2 ! 0 3 0 10 :484
- 7 - A 20 OR2 0 3 0 1 :487
- 8 - A 18 OR2 ! 0 3 0 9 :494
- 8 - A 20 OR2 0 3 0 1 :497
- 5 - A 15 OR2 0 3 0 1 :503
- 6 - A 15 OR2 0 3 0 1 :506
- 7 - A 15 OR2 0 3 0 1 :509
- 8 - A 15 OR2 0 3 0 1 :512
- 2 - A 15 OR2 0 3 0 1 :515
- 2 - A 23 OR2 0 3 0 1 :521
- 3 - A 23 OR2 0 3 0 1 :524
- 4 - A 23 OR2 0 3 0 1 :527
- 5 - A 23 OR2 0 3 0 1 :530
- 6 - A 23 OR2 0 3 0 1 :533
- 4 - A 16 OR2 0 3 0 1 :539
- 5 - A 16 OR2 0 3 0 1 :542
- 6 - A 16 OR2 0 3 0 1 :545
- 7 - A 16 OR2 0 3 0 1 :548
- 2 - A 12 OR2 0 3 0 1 :557
- 3 - A 12 OR2 0 3 0 1 :560
- 4 - A 12 OR2 0 3 0 1 :563
- 5 - A 12 OR2 0 3 0 1 :566
- 6 - A 12 OR2 0 3 0 1 :569
- 3 - A 04 OR2 0 3 0 1 :575
- 4 - A 04 OR2 0 3 0 1 :578
- 5 - A 04 OR2 0 3 0 1 :581
- 6 - A 04 OR2 0 3 0 1 :584
- 4 - A 02 OR2 0 3 0 1 :593
- 5 - A 02 OR2 0 3 0 1 :596
- 6 - A 02 OR2 0 3 0 1 :599
- 7 - A 02 OR2 0 3 0 1 :602
- 7 - A 18 AND2 s ! 0 3 0 4 ~641~1
- 5 - A 14 OR2 0 3 0 1 :668
- 3 - A 14 OR2 0 3 0 1 :686
- 8 - A 12 OR2 ! 0 3 0 8 :800
- 3 - A 22 OR2 ! 0 3 0 4 :948
- 1 - A 22 OR2 0 4 0 1 :1176
- 7 - A 22 OR2 0 4 0 1 :1182
- 8 - A 23 OR2 0 4 0 1 :1188
- 7 - A 12 OR2 0 4 0 1 :1200
- 2 - A 22 OR2 s 0 3 0 6 ~1308~1
- 8 - A 16 OR2 0 4 0 1 :1325
- 7 - A 04 OR2 0 4 0 1 :1337
- 4 - A 22 AND2 s 0 2 0 2 ~1338~1
- 8 - A 02 OR2 0 4 0 1 :1343
- 4 - A 11 OR2 s 0 4 0 1 ~1348~1
- 5 - A 11 OR2 s 0 4 0 1 ~1348~2
- 6 - A 11 OR2 s 0 4 0 1 ~1348~3
- 8 - A 11 OR2 s 0 4 0 1 ~1348~4
- 6 - A 14 OR2 s 0 3 0 1 ~1361~1
- 3 - A 20 AND2 1 0 0 1 :1436
- 4 - A 15 OR2 1 0 0 1 :1445
- 1 - A 24 AND2 1 0 0 1 :1454
- 3 - A 16 OR2 1 0 0 1 :1463
- 1 - A 01 AND2 1 0 0 1 :1472
- 2 - A 04 OR2 1 0 0 1 :1481
- 3 - A 02 AND2 1 0 0 1 :1490
- 3 - A 11 OR2 1 0 0 1 :1499
- 2 - A 20 AND2 1 0 0 1 :1508
- 1 - A 15 AND2 1 0 0 1 :1517
- 1 - A 23 AND2 1 0 0 1 :1526
- 1 - A 16 OR2 1 0 0 1 :1535
- 1 - A 08 AND2 1 0 0 1 :1544
- 1 - A 04 AND2 1 0 0 1 :1553
- 1 - A 02 AND2 1 0 0 1 :1562
- 2 - A 11 AND2 1 0 0 1 :1571
- 1 - A 17 AND2 1 0 0 1 :1580
- 3 - A 15 AND2 1 0 0 1 :1589
- 4 - A 13 OR2 1 0 0 1 :1598
- 1 - A 21 OR2 1 0 0 1 :1607
- 1 - A 10 AND2 1 0 0 1 :1616
- 1 - A 03 AND2 1 0 0 1 :1625
- 1 - A 06 AND2 1 0 0 1 :1634
- 1 - A 11 AND2 1 0 0 1 :1643
- 1 - B 03 DFFE + 0 2 0 16 tempb (:1701)
- 1 - B 05 AND2 0 3 0 8 :2062
- 4 - B 10 OR2 0 3 0 1 :2065
- 8 - B 05 OR2 ! 0 3 0 8 :2072
- 5 - B 10 OR2 0 3 0 1 :2075
- 6 - B 05 AND2 0 3 0 8 :2082
- 6 - B 10 OR2 0 3 0 1 :2085
- 5 - B 05 AND2 0 3 0 11 :2092
- 7 - B 10 OR2 0 3 0 1 :2095
- 4 - B 02 OR2 0 3 0 1 :2104
- 5 - B 02 OR2 0 3 0 1 :2107
- 6 - B 02 OR2 0 3 0 1 :2110
- 7 - B 02 OR2 0 3 0 1 :2113
- 4 - B 09 OR2 0 3 0 1 :2122
- 5 - B 09 OR2 0 3 0 1 :2125
- 6 - B 09 OR2 0 3 0 1 :2128
- 7 - B 09 OR2 0 3 0 1 :2131
- 4 - B 08 OR2 0 3 0 1 :2140
- 6 - B 08 OR2 0 3 0 1 :2143
- 7 - B 08 OR2 0 3 0 1 :2146
- 3 - B 23 OR2 0 3 0 1 :2158
- 4 - B 23 OR2 0 3 0 1 :2161
- 6 - B 23 OR2 0 3 0 1 :2164
- 7 - B 23 OR2 0 3 0 1 :2167
- 5 - B 16 OR2 0 3 0 1 :2176
- 6 - B 16 OR2 0 3 0 1 :2179
- 7 - B 16 OR2 0 3 0 1 :2182
- 5 - B 17 OR2 0 3 0 1 :2194
- 6 - B 17 OR2 0 3 0 1 :2197
- 7 - B 17 OR2 0 3 0 1 :2200
- 4 - B 14 OR2 0 3 0 1 :2212
- 5 - B 14 OR2 0 3 0 1 :2215
- 6 - B 14 OR2 0 3 0 1 :2218
- 8 - B 14 OR2 0 3 0 1 :2221
- 2 - B 05 OR2 ! 0 4 0 1 :2241
- 2 - B 03 OR2 0 4 0 1 :2272
- 2 - B 23 OR2 ! 0 3 0 8 :2398
- 2 - B 10 OR2 ! 0 3 0 4 :2546
- 8 - B 10 OR2 0 4 0 1 :2774
- 8 - B 02 OR2 0 4 0 1 :2780
- 8 - B 09 OR2 0 4 0 1 :2786
- 8 - B 23 OR2 0 4 0 1 :2798
- 5 - B 03 OR2 s 0 3 0 6 ~2906~1
- 8 - B 08 OR2 0 4 0 1 :2923
- 8 - B 16 OR2 0 4 0 1 :2935
- 3 - B 03 AND2 s 0 2 0 2 ~2936~1
- 8 - B 17 OR2 0 4 0 1 :2941
- 7 - B 03 OR2 s 0 4 0 1 ~2959~1
- 2 - B 01 AND2 1 0 0 1 :3034
- 1 - B 12 OR2 1 0 0 1 :3043
- 1 - B 09 AND2 1 0 0 1 :3052
- 1 - B 08 AND2 1 0 0 1 :3061
- 1 - B 13 AND2 1 0 0 1 :3070
- 2 - B 16 AND2 1 0 0 1 :3079
- 1 - B 17 AND2 1 0 0 1 :3088
- 1 - B 14 AND2 1 0 0 1 :3097
- 3 - B 10 AND2 1 0 0 1 :3106
- 3 - B 02 OR2 1 0 0 1 :3115
- 1 - B 04 AND2 1 0 0 1 :3124
- 3 - B 08 OR2 1 0 0 1 :3133
- 1 - B 22 AND2 1 0 0 1 :3142
- 4 - B 16 AND2 1 0 0 1 :3151
- 4 - B 17 AND2 1 0 0 1 :3160
- 3 - B 14 AND2 1 0 0 1 :3169
- 1 - B 07 AND2 1 0 0 1 :3178
- 2 - B 02 AND2 1 0 0 1 :3187
- 3 - B 09 AND2 1 0 0 1 :3196
- 2 - B 08 AND2 1 0 0 1 :3205
- 1 - B 23 AND2 1 0 0 1 :3214
- 3 - B 16 OR2 1 0 0 1 :3223
- 2 - B 17 AND2 1 0 0 1 :3232
- 2 - B 14 OR2 1 0 0 1 :3241
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\work\vhdl\jiaotongdeng\traffic_con.rpt
traffic_con
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 24/ 96( 25%) 6/ 48( 12%) 9/ 48( 18%) 0/16( 0%) 10/16( 62%) 0/16( 0%)
B: 20/ 96( 20%) 9/ 48( 18%) 5/ 48( 10%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\work\vhdl\jiaotongdeng\traffic_con.rpt
traffic_con
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 30 clk
Device-Specific Information: d:\work\vhdl\jiaotongdeng\traffic_con.rpt
traffic_con
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 78 reset
Device-Specific Information: d:\work\vhdl\jiaotongdeng\traffic_con.rpt
traffic_con
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is ':41' = 'counta0'
-- Equation name is 'counta0', location is LC7_A11, type is buried.
counta0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL( reset), VCC, VCC);
_EQ001 = _LC8_A11 & !tempa
# !counta0 & _LC2_A22;
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