📄 mux4.rpt
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Device-Specific Information: d:\work\vhdl\jiaotongdeng\mux4.rpt
mux4
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 13/ 96( 13%) 0/ 48( 0%) 7/ 48( 14%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\work\vhdl\jiaotongdeng\mux4.rpt
mux4
** EQUATIONS **
ina0 : INPUT;
ina1 : INPUT;
ina2 : INPUT;
ina3 : INPUT;
ina4 : INPUT;
ina5 : INPUT;
ina6 : INPUT;
ina7 : INPUT;
inb0 : INPUT;
inb1 : INPUT;
inb2 : INPUT;
inb3 : INPUT;
inb4 : INPUT;
inb5 : INPUT;
inb6 : INPUT;
inb7 : INPUT;
sel0 : INPUT;
sel1 : INPUT;
sel2 : INPUT;
-- Node name is 'dout0'
-- Equation name is 'dout0', type is output
dout0 = _LC8_B24;
-- Node name is 'dout1'
-- Equation name is 'dout1', type is output
dout1 = _LC7_B21;
-- Node name is 'dout2'
-- Equation name is 'dout2', type is output
dout2 = _LC3_B21;
-- Node name is 'dout3'
-- Equation name is 'dout3', type is output
dout3 = _LC5_B13;
-- Node name is ':181'
-- Equation name is '_LC6_B24', type is buried
_LC6_B24 = LCELL( _EQ001);
_EQ001 = sel0 & sel1 & sel2;
-- Node name is ':184'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = LCELL( _EQ002);
_EQ002 = _LC5_B13 & !_LC6_B24
# inb3 & _LC6_B24;
-- Node name is ':191'
-- Equation name is '_LC5_B24', type is buried
_LC5_B24 = LCELL( _EQ003);
_EQ003 = !sel0 & sel1 & sel2;
-- Node name is ':194'
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = LCELL( _EQ004);
_EQ004 = _LC1_B13 & !_LC5_B24
# inb7 & _LC5_B24;
-- Node name is ':201'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = LCELL( _EQ005);
_EQ005 = sel0 & !sel1 & !sel2;
-- Node name is ':204'
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = LCELL( _EQ006);
_EQ006 = _LC2_B13 & !_LC2_B24
# ina3 & _LC2_B24;
-- Node name is ':211'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = LCELL( _EQ007);
_EQ007 = !sel0 & !sel1 & !sel2;
-- Node name is ':214'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = LCELL( _EQ008);
_EQ008 = !_LC1_B24 & _LC3_B13
# ina7 & _LC1_B24;
-- Node name is ':220'
-- Equation name is '_LC5_B21', type is buried
_LC5_B21 = LCELL( _EQ009);
_EQ009 = _LC3_B21 & !_LC6_B24
# inb2 & _LC6_B24;
-- Node name is ':223'
-- Equation name is '_LC6_B21', type is buried
_LC6_B21 = LCELL( _EQ010);
_EQ010 = _LC5_B21 & !_LC5_B24
# inb6 & _LC5_B24;
-- Node name is ':226'
-- Equation name is '_LC8_B21', type is buried
_LC8_B21 = LCELL( _EQ011);
_EQ011 = !_LC2_B24 & _LC6_B21
# ina2 & _LC2_B24;
-- Node name is ':229'
-- Equation name is '_LC3_B21', type is buried
_LC3_B21 = LCELL( _EQ012);
_EQ012 = !_LC1_B24 & _LC8_B21
# ina6 & _LC1_B24;
-- Node name is ':235'
-- Equation name is '_LC1_B21', type is buried
_LC1_B21 = LCELL( _EQ013);
_EQ013 = !_LC6_B24 & _LC7_B21
# inb1 & _LC6_B24;
-- Node name is ':238'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = LCELL( _EQ014);
_EQ014 = _LC1_B21 & !_LC5_B24
# inb5 & _LC5_B24;
-- Node name is ':241'
-- Equation name is '_LC4_B21', type is buried
_LC4_B21 = LCELL( _EQ015);
_EQ015 = _LC2_B21 & !_LC2_B24
# ina1 & _LC2_B24;
-- Node name is ':244'
-- Equation name is '_LC7_B21', type is buried
_LC7_B21 = LCELL( _EQ016);
_EQ016 = !_LC1_B24 & _LC4_B21
# ina5 & _LC1_B24;
-- Node name is ':250'
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ017);
_EQ017 = !_LC6_B24 & _LC8_B24
# inb0 & _LC6_B24;
-- Node name is ':253'
-- Equation name is '_LC4_B24', type is buried
_LC4_B24 = LCELL( _EQ018);
_EQ018 = _LC3_B24 & !_LC5_B24
# inb4 & _LC5_B24;
-- Node name is ':256'
-- Equation name is '_LC7_B24', type is buried
_LC7_B24 = LCELL( _EQ019);
_EQ019 = !_LC2_B24 & _LC4_B24
# ina0 & _LC2_B24;
-- Node name is ':259'
-- Equation name is '_LC8_B24', type is buried
_LC8_B24 = LCELL( _EQ020);
_EQ020 = !_LC1_B24 & _LC7_B24
# ina4 & _LC1_B24;
Project Information d:\work\vhdl\jiaotongdeng\mux4.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:02
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,127K
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