tb_top.v

该程序是在xilinx的FPGA上实现DDR_SDRAM接口

/******************************************************************************
 *
 *    File Name:  tb_top.v
 *      Version:  1.0
 *         Date:  Jan 12, 2001
 * 
 *  Description:  Functional test bench.
 * 
 *       Author:  Jennnifer Tran and Ratima Kataria
 *      Company:  Xilinx
 *
 *                Copyright (c) 1999 Xilinx, Inc.
 *                All rights reserved
 *
 *    DDR SDRAM:  64M (1M x 16Bit x 4Bank)
 * 
 *   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
 *                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
 *                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
 *                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
 *
 ******************************************************************************/

`timescale 1ns / 1ps 
`define PERIOD       7.5
`define HALF_PERIOD  `PERIOD/2      
`define DELAY_TIME        `PERIOD/10

// define.v

`define T_RCD 2   //ras to cas delay, for -8 SDRAM, we need 3 clock cycles for t_rcd

`define DDR_ADDR_MSB           11
`define DDR_DATA_MSB           15
`define SYS_ADDR_MSB           21
`define SYS_DATA_MSB           31
`define U_ADDR_MSB             21
`define U_DATA_MSB             31
`define ROW_ADDR_MSB           11
`define COL_ADDR_MSB           	7
`define ENABLE_MSB           	3

//system commands: sys_cmd[7:1]
`define sys_nop                7'b0000001
`define sys_load_mr            7'b0000010
`define sys_read               7'b0000100
`define sys_write              7'b0001000
`define sys_precharge          7'b0010000
`define sys_refresh            7'b0100000
`define sys_burst_stop         7'b1000000

`define SYS_NOP                1
`define SYS_LOAD_MR            2
`define SYS_READ               3
`define SYS_WRITE              4
`define SYS_PRECHARGE          5
`define SYS_REFRESH            6
`define SYS_BURST_STOP         7

   //controller states
`define CTLR_IDLE              1
`define CTLR_REFRESH           2
`define CTLR_PRECHARGE         3
`define CTLR_LOAD_MR           4
`define CTLR_ACT               5
`define CTLR_ACT_WAIT          6               
`define CTLR_READ              7
`define CTLR_WRITE             8
`define CTLR_READ_WAIT         9
`define CTLR_READ_DATA         10
`define CTLR_WRITE_DATA        11

   //DDR commands
`define DDR_LOAD_MR            3'b000
`define DDR_AUTO_REFRESH       3'b001
`define DDR_PRECHARGE          3'b010
`define DDR_ACT                3'b011
`define DDR_WRITEA             3'b100
`define DDR_READA              3'b101
`define DDR_BURST_STOP         3'b110
`define DDR_NOP                3'b111

// end of define.v

module test();   
   reg [`SYS_ADDR_MSB:0] sys_addr;
   reg [7:1] 		 sys_cmd;
   reg 			 sys_reset_n;
   reg 			 sys_clk;
   reg [`SYS_DATA_MSB:0] sys_data_i;
   
   wire [`DDR_ADDR_MSB:0] ddr_ad;
   wire [`DDR_DATA_MSB:0] ddr_dq; 
   wire [1:0] 		  ddr_dm;
   wire [1:0] 		  ddr_ba;
   wire [1:0] 		  ddr_dqs;
   wire 		  ddr_rasb;
   wire 		  ddr_casb;
   wire 		  ddr_web;

	wire [`DDR_ADDR_MSB:0] ddr_ad_sig;
	wire 		  ddr_rasb_sig;
	wire 		  ddr_casb_sig;
	wire 		  ddr_web_sig;
	wire [`DDR_DATA_MSB:0] ddr_dq_sig; 
   	wire [1:0] 		  ddr_dm_sig;
   	wire [1:0] 		  ddr_ba_sig;
   	wire [1:0] 		  ddr_dqs_sig;

   wire [`SYS_DATA_MSB:0] sys_data_o;
   
 //  reg 			  GSR;
   
//`include "string_decode_fn.v"

   top utt(.ddr_ad(ddr_ad), .ddr_dm(ddr_dm), .ddr_ba(ddr_ba), 
	   .ddr_rasb(ddr_rasb), .ddr_casb(ddr_casb), .ddr_web(ddr_web), 
	   .ddr_clk(ddr_clk), .ddr_clkb(ddr_clkb), .ddr_dqs(ddr_dqs), 
	   .ddr_csb(ddr_csb), .ddr_cke(ddr_cke), 
	   .ddr_dq(ddr_dq_sig), 
	   .sys_addr(sys_addr), .sys_data_i(sys_data_i), 
	   .sys_cmd(sys_cmd), .sys_reset_n(sys_reset_n), .sys_clk(sys_clk), 
	   .sys_clk_fb(sys_clk_fb), .sys_data_o(sys_data_o), .sys_ref_ack(sys_ref_ack),
	   .sys_data_valid(sys_data_valid)
	   );

   assign  sys_clk_fb = ddr_clk;  //feed DDR clock back to FPGA 
   
   mt46v4m16 u_ddr (.Clk(ddr_clk), .Clk_n(ddr_clkb), .Cs_n(ddr_csb), 
	      .Cke(ddr_cke), .Ba(ddr_ba_sig), .Addr(ddr_ad_sig), 
	      .Ras_n(ddr_rasb_sig), .Cas_n(ddr_casb_sig), .We_n(ddr_web_sig), 
	      .Dm(ddr_dm_sig), .Dq(ddr_dq_sig), .Dqs(ddr_dqs_sig[0]));
  
	assign #1 ddr_casb_sig = ddr_casb;
	assign #1 ddr_rasb_sig = ddr_rasb;
	assign #1 ddr_web_sig = ddr_web;
	assign #1 ddr_ad_sig = ddr_ad;
	assign #1 ddr_ba_sig = ddr_ba;
	assign #1 ddr_dm_sig = ddr_dm;
	assign #1 ddr_dq_sig = ddr_dq;
	assign #1 ddr_dqs_sig = ddr_dqs;

   always #(`HALF_PERIOD) sys_clk <= ~sys_clk;

   //at startup, all flip-flops would be reset by GSR
   //simulate GSR function
   initial begin
      force utt.I_ddr_ctlr.cslt_cntr.count = 3'b000;
      #1;
      release utt.I_ddr_ctlr.cslt_cntr.count;
   end
   
   initial begin
      sys_cmd = 7'b0000000;
      sys_addr = 22'h00000;
      sys_data_i = 32'h0000000;
      sys_clk = 0;
      sys_reset_n = 1;
      sys_cmd[`SYS_NOP] = 1;
     
      
      #(32*`PERIOD);   //wait for DLL in FPGA to lock
      #(`HALF_PERIOD); //delay inputs to avoid race condition
      #(`DELAY_TIME); precharge_all_banks;
      #(5*`PERIOD);     nop;
      #(`PERIOD);     EMRS;
      
      run_test(3'b011,3'b010); // burst = 8, cas latency = 2;
      run_test(3'b011,3'b110); // burst = 8, cas latency = 2.5;
		     
      run_test(3'b010,3'b010); // burst = 4, cas latency = 2;
      run_test(3'b010,3'b110); // burst = 4, cas latency = 2.5;
		     
      run_test(3'b001,3'b010); // burst = 2, cas latency = 2;
      run_test(3'b001,3'b110); // burst = 2, cas latency = 2.5;

      $finish;
   end // initial begin
   
   task run_test;
      input [2:0] burst_length;
      input [2:0] cas_latency;
      begin
	 #(`PERIOD);     nop;
	 #(`PERIOD);     MRS(burst_length,0,cas_latency); 
	 #(`PERIOD);     nop;
	 #(`PERIOD);     precharge_all_banks;
	 #(`PERIOD);     nop;
	 #(2*`PERIOD);   auto_refresh;
	 #(`PERIOD);     nop;
	 #(6*`PERIOD);   auto_refresh;
	 #(`PERIOD);     nop;
	 //write_autoprecharge (ba,row_addr,col_addr,write_data1,write_data2,write_data3,write_data4)
	 #(6*`PERIOD);   write_autoprecharge(2'b00, 12'h200, 8'h10, 32'h10102020, 32'h03030404, 32'h50506060, 32'h07070808);
	 #(`PERIOD);     nop;
	 #(10*`PERIOD);  read_autoprecharge(2'b00, 12'h200, 8'h10);
	 #(9*`PERIOD);   nop;
	 #(10*`PERIOD);  write_autoprecharge(2'b01, 12'h200, 8'h20, 32'h09876543, 32'h98765432, 32'h87654321, 32'h76543210);
	 #(`PERIOD);     nop;
	 #(10*`PERIOD);  read_autoprecharge(2'b00, 12'h200, 8'h10);
	 #(9*`PERIOD);   nop;
	 #(10*`PERIOD);  read_autoprecharge(2'b01, 12'h200, 8'h20);
	 #(9*`PERIOD);   nop;
	 #(10*`PERIOD);
      end
   endtask // run_test   

   task EMRS;
      begin
	 sys_cmd = `sys_load_mr;
	 sys_addr = {22'h10_0000};  //ba0 = 1, sys_ad[20] = 1
      end
   endtask // EMRS   

   task MRS;
      input [2:0] burst_length;
      input 	     burst_type;
      input [2:0] cas_latency;
      begin
	 sys_cmd = `sys_load_mr;
	 sys_addr = {12'h000,1'b0,cas_latency,burst_type,burst_length};
      end
   endtask // MRS

   task auto_refresh;
      begin
	 sys_cmd = `sys_refresh;
	 #(`PERIOD);
	 sys_cmd = `sys_nop;
      end
   endtask // auto_refresh

   task read_autoprecharge;
      input [1:0]  ba;
      input [`ROW_ADDR_MSB:0] row_addr;
      input [`COL_ADDR_MSB:0] col_addr;
      begin
	 sys_cmd = `sys_read;
	 sys_addr = {ba,row_addr,col_addr};
	 #(`PERIOD);
	 sys_cmd = `sys_nop;
	 #(9*`PERIOD);
      end
   endtask // read_autoprecharge

   task write_autoprecharge; //for burst length = 4
      input [1:0]  ba;
      input [`ROW_ADDR_MSB:0] row_addr;
      input [`COL_ADDR_MSB:0] col_addr;
      input [`SYS_DATA_MSB:0] write_data1,write_data2,write_data3,write_data4;
      begin	 
	 sys_cmd = `sys_write;
	 sys_addr = {ba,row_addr,col_addr};
	 sys_data_i = write_data1;
	 #(`PERIOD);  
	 sys_data_i = write_data2;
	 #(`PERIOD);  
	 sys_data_i = write_data3;
	 #(`PERIOD);  
	 sys_data_i = write_data4;
      end
   endtask // write_autoprecharge
   task burst_stop;
      sys_cmd = `sys_burst_stop;
   endtask // burst_stop

   task precharge_all_banks;
      begin      
	 sys_cmd = `sys_precharge;
      end
   endtask // precharge

   task nop;
      sys_cmd = `sys_nop;
   endtask // nop
   

   //for virsim
   //initial $vcdpluson(test);
   

endmodule