string_decode_fn.v

该程序是在xilinx的FPGA上实现DDR_SDRAM接口

`define T_RCD 2   //ras to cas delay, for -8 SDRAM, we need 3 clock cycles for t_rcd

`define DDR_ADDR_MSB           11
`define DDR_DATA_MSB           15
`define SYS_ADDR_MSB           21
`define SYS_DATA_MSB           31
`define U_ADDR_MSB             21
`define U_DATA_MSB             31
`define ROW_ADDR_MSB           11
`define COL_ADDR_MSB           	7
`define ENABLE_MSB           	3

//system commands: sys_cmd[7:1]
`define sys_nop                7'b0000001
`define sys_load_mr            7'b0000010
`define sys_read               7'b0000100
`define sys_write              7'b0001000
`define sys_precharge          7'b0010000
`define sys_refresh            7'b0100000
`define sys_burst_stop         7'b1000000

`define SYS_NOP                1
`define SYS_LOAD_MR            2
`define SYS_READ               3
`define SYS_WRITE              4
`define SYS_PRECHARGE          5
`define SYS_REFRESH            6
`define SYS_BURST_STOP         7

   //controller states
`define CTLR_IDLE              1
`define CTLR_REFRESH           2
`define CTLR_PRECHARGE         3
`define CTLR_LOAD_MR           4
`define CTLR_ACT               5
`define CTLR_ACT_WAIT          6               
`define CTLR_READ              7
`define CTLR_WRITE             8
`define CTLR_READ_WAIT         9
`define CTLR_READ_DATA         10
`define CTLR_WRITE_DATA        11

   //DDR commands
`define DDR_LOAD_MR            3'b000
`define DDR_AUTO_REFRESH       3'b001
`define DDR_PRECHARGE          3'b010
`define DDR_ACT                3'b011
`define DDR_WRITEA             3'b100
`define DDR_READA              3'b101
`define DDR_BURST_STOP         3'b110
`define DDR_NOP                3'b111



reg [8*25 :1] string_u_cmd, string_sys_cmd, string_state, string_next_state, string_ddr_cmd, string_next_ddr_cmd;

always @(utt.I_ddr_ctlr.u_cmd) begin
   case (1)
     utt.I_ddr_ctlr.u_cmd[`SYS_REFRESH]            : string_u_cmd = "REFRESH";
     utt.I_ddr_ctlr.u_cmd[`SYS_NOP]                : string_u_cmd = "NOP";
     utt.I_ddr_ctlr.u_cmd[`SYS_PRECHARGE]          : string_u_cmd = "PRECHARGE";
     utt.I_ddr_ctlr.u_cmd[`SYS_LOAD_MR]            : string_u_cmd = "LOAD_MR";
     utt.I_ddr_ctlr.u_cmd[`SYS_READ]               : string_u_cmd = "READ";
     utt.I_ddr_ctlr.u_cmd[`SYS_WRITE]              : string_u_cmd = "WRITE";
     utt.I_ddr_ctlr.u_cmd[`SYS_BURST_STOP]         : string_u_cmd = "BURST_STOP";
     default: string_u_cmd = "UNKNOWN";
   endcase // case(u_cmd)
end // always @ (u_cmd)
   
always @(sys_cmd) begin
   case (1)
     sys_cmd[`SYS_REFRESH]            : string_sys_cmd = "REFRESH";
     sys_cmd[`SYS_NOP]                : string_sys_cmd = "NOP";
     sys_cmd[`SYS_PRECHARGE]          : string_sys_cmd = "PRECHARGE";
     sys_cmd[`SYS_LOAD_MR]            : string_sys_cmd = "LOAD_MR";
     sys_cmd[`SYS_READ]               : string_sys_cmd = "READ";
     sys_cmd[`SYS_WRITE]              : string_sys_cmd = "WRITE";
     sys_cmd[`SYS_BURST_STOP]         : string_sys_cmd = "BURST_STOP";
     default: string_sys_cmd = "UNKNOWN";
   endcase // case(sys_cmd)
end // always @ (sys_cmd)
   
   wire state12 = 	utt.I_ddr_ctlr.controller.state[12];
   wire state11 = 	utt.I_ddr_ctlr.controller.state[11];
   wire state10 = 	utt.I_ddr_ctlr.controller.state[10];
   wire state9 = 	utt.I_ddr_ctlr.controller.state[9];
   wire state8 = 	utt.I_ddr_ctlr.controller.state[8];
   wire state7 = 	utt.I_ddr_ctlr.controller.state[7];
   wire state6 = 	utt.I_ddr_ctlr.controller.state[6];
   wire state5 = 	utt.I_ddr_ctlr.controller.state[5];
   wire state4 = 	utt.I_ddr_ctlr.controller.state[4];
   wire state3 = 	utt.I_ddr_ctlr.controller.state[3];
   wire state2 = 	utt.I_ddr_ctlr.controller.state[2];
   wire state1 = 	utt.I_ddr_ctlr.controller.state[1];
   wire [12:1] state = {state12, state11, state10, state9, state8, state7, state6, state5, state4, state3, state2, state1};
   always @(state) begin
	case (1'b1)					   
	  state1      : string_state = "IDLE";
	  state2      : string_state = "REFRESH";
	  state3      : string_state = "PRECHARGE";
	  state4      : string_state = "LOAD_MR";
	  state5      : string_state = "ACT";
	  state6      : string_state = "ACT_WAIT";
	  state7      : string_state = "READ";
	  state8      : string_state = "WRITE";
	  state9      : string_state = "READ_WAIT";
	  state10     : string_state = "READ_DATA";
	  state11     : string_state = "WRITE_DATA";
	  default: string_state = "UNKOWN";
	endcase // case(state)
   end

   wire next_state12 = 	utt.I_ddr_ctlr.controller.next_state[11];
   wire next_state11 = 	utt.I_ddr_ctlr.controller.next_state[11];   
   wire next_state10 = 	utt.I_ddr_ctlr.controller.next_state[10];
   wire next_state9 = 	utt.I_ddr_ctlr.controller.next_state[9];
   wire next_state8 = 	utt.I_ddr_ctlr.controller.next_state[8];
   wire next_state7 = 	utt.I_ddr_ctlr.controller.next_state[7];
   wire next_state6 = 	utt.I_ddr_ctlr.controller.next_state[6];
   wire next_state5 = 	utt.I_ddr_ctlr.controller.next_state[5];
   wire next_state4 = 	utt.I_ddr_ctlr.controller.next_state[4];
   wire next_state3 = 	utt.I_ddr_ctlr.controller.next_state[3];
   wire next_state2 = 	utt.I_ddr_ctlr.controller.next_state[2];
   wire next_state1 = 	utt.I_ddr_ctlr.controller.next_state[1];
   wire [12:1] next_state = {next_state12, next_state11, next_state10, next_state9, next_state8, next_state7, next_state6, next_state5, next_state4, next_state3, next_state2, next_state1};
   always @(next_state) begin
	case (1'b1)					   
	  next_state1	     : string_next_state = "IDLE";
	  next_state2	     : string_next_state = "REFRESH";
	  next_state3	     : string_next_state = "PRECHARGE";
	  next_state4	     : string_next_state = "LOAD_MR";
	  next_state5	     : string_next_state = "ACT";
	  next_state6	     : string_next_state = "ACT_WAIT";
	  next_state7	     : string_next_state = "READ";
	  next_state8	     : string_next_state = "WRITE";
	  next_state9	     : string_next_state = "BURST_STOP";
	  next_state10          : string_next_state = "READ_WAIT";
	  next_state11         : string_next_state = "READ_DATA";
	  next_state12         : string_next_state = "WRITE_DATA";
	  default              :string_next_state = "UNKOWN";
	endcase // case(next_state)
   end

   wire [2:0] ddr_cmd = {ddr_rasb, ddr_casb, ddr_web};
   always @(ddr_cmd) begin
      case (ddr_cmd)
	`DDR_LOAD_MR           : string_ddr_cmd = "LOAD_MR";
	`DDR_AUTO_REFRESH      : string_ddr_cmd = "AUTO_REFRESH";
	`DDR_PRECHARGE         : string_ddr_cmd = "PRECHARGE";
	`DDR_ACT               : string_ddr_cmd = "ACT";
	`DDR_WRITEA            : string_ddr_cmd = "WRITEA";
	`DDR_READA             : string_ddr_cmd = "READA";
	`DDR_BURST_STOP        : string_ddr_cmd = "BURST_STOP";
	`DDR_NOP               : string_ddr_cmd = "NOP";
	default: string_ddr_cmd = "UNKOWN";
      endcase // case(ddr_cmd)
   end // always @ (ddr_cmd)