i2c_slave.vcd

完整的I2C slave model以及spec詳附在內,適合想利用verilog開發此類傳輸的人參考

$date
	Tue Feb 08 04:33:43 2005
$end
$version
	ModelSim Version 5.8
$end
$timescale
	10ps
$end
$scope module top $end
$var wire 1 ! sda_o $end
$var reg 1 " scl $end
$var reg 1 # sda_i $end
$var reg 1 $ sda_oe $end
$var reg 1 % nrst $end
$var reg 1 & clk $end
$scope task idle $end
$var reg 3 ' num [2:0] $end
$var integer 32 ( i $end
$upscope $end
$scope task Release_bus $end
$upscope $end
$scope task start $end
$upscope $end
$scope task stop $end
$upscope $end
$scope task trans_bit $end
$var reg 1 ) bit $end
$upscope $end
$scope task issue_command $end
$var reg 1 * rd_wr $end
$upscope $end
$scope task ack2slave $end
$upscope $end
$scope task wait_slaves_ack $end
$upscope $end
$scope task write_addr $end
$var reg 7 + addr [6:0] $end
$var integer 32 , i $end
$upscope $end
$scope task write_data $end
$var reg 8 - data [7:0] $end
$var integer 32 . i $end
$upscope $end
$scope task read_data $end
$var integer 32 / i $end
$upscope $end
$scope task single_transfer $end
$var reg 1 0 rd_wr $end
$var reg 7 1 addr [6:0] $end
$var reg 8 2 data [7:0] $end
$upscope $end
$scope task burst_transfer $end
$var reg 3 3 burst [2:0] $end
$var reg 1 4 rd_wr $end
$var reg 7 5 start_addr [6:0] $end
$var reg 40 6 data [39:0] $end
$var integer 32 7 i $end
$var reg 3 8 indx [2:0] $end
$upscope $end
$scope module i2c_slave $end
$var wire 1 9 scl $end
$var wire 1 : sda_i $end
$var wire 1 ; sda_oe $end
$var wire 1 ! sda_o $end
$var reg 1 < start $end
$var reg 1 = stop $end
$var reg 1 > rd $end
$var reg 1 ? wr $end
$var integer 32 @ i $end
$var reg 1 A sda $end
$var reg 7 B addr [6:0] $end
$var reg 8 C temp [7:0] $end
$var reg 1 D tmp $end
$var reg 1 E wp $end
$var reg 1 F continue $end
$var reg 1 G burst $end
$var reg 4 H index [3:0] $end
$var wire 1 I test1 [7] $end
$var wire 1 J test1 [6] $end
$var wire 1 K test1 [5] $end
$var wire 1 L test1 [4] $end
$var wire 1 M test1 [3] $end
$var wire 1 N test1 [2] $end
$var wire 1 O test1 [1] $end
$var wire 1 P test1 [0] $end
$var wire 1 Q test2 [7] $end
$var wire 1 R test2 [6] $end
$var wire 1 S test2 [5] $end
$var wire 1 T test2 [4] $end
$var wire 1 U test2 [3] $end
$var wire 1 V test2 [2] $end
$var wire 1 W test2 [1] $end
$var wire 1 X test2 [0] $end
$var wire 1 Y test3 [7] $end
$var wire 1 Z test3 [6] $end
$var wire 1 [ test3 [5] $end
$var wire 1 \ test3 [4] $end
$var wire 1 ] test3 [3] $end
$var wire 1 ^ test3 [2] $end
$var wire 1 _ test3 [1] $end
$var wire 1 ` test3 [0] $end
$var wire 1 a test4 [7] $end
$var wire 1 b test4 [6] $end
$var wire 1 c test4 [5] $end
$var wire 1 d test4 [4] $end
$var wire 1 e test4 [3] $end
$var wire 1 f test4 [2] $end
$var wire 1 g test4 [1] $end
$var wire 1 h test4 [0] $end
$var wire 1 i test5 [7] $end
$var wire 1 j test5 [6] $end
$var wire 1 k test5 [5] $end
$var wire 1 l test5 [4] $end
$var wire 1 m test5 [3] $end
$var wire 1 n test5 [2] $end
$var wire 1 o test5 [1] $end
$var wire 1 p test5 [0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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$end
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