plus.vhd

这是一个用VHDL层次化设计的一个九九乘法表源文件,还包含仿真波形

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY plus IS
PORT(a:IN INTEGER RANGE 0 TO 9;
b:IN INTEGER RANGE 0 TO 9;
m:OUT INTEGER RANGE 0 TO 81);
END plus;

ARCHITECTURE XYB OF plus IS
BEGIN
   m<=a*b;
END XYB;