count8.vhd

来自「这是一个用VHDL层次化设计的一个九九乘法表源文件,还包含仿真波形」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY COUNT8 IS
PORT(CLK : IN STD_LOGIC;
	 CRT,ENT:IN STD_LOGIC;
 	 TT:OUT STD_LOGIC);
END;

ARCHITECTURE XYB OF COUNT8 IS
BEGIN
	PROCESS(CLK)
	VARIABLE COUNT:INTEGER RANGE 0 TO 7;
	BEGIN
		IF CLK'EVENT AND CLK='1' THEN
			IF CRT='1' AND ENT='1' THEN
				IF COUNT=7 THEN
					COUNT:=0;
					TT<='1';
				ELSE
					COUNT:=COUNT+1;
					TT<='0';
				END IF;
			END IF;
		END IF;
	END PROCESS;
END XYB;