plus_lib.vhd

来自「这是一个用VHDL层次化设计的一个九九乘法表源文件,还包含仿真波形」· VHDL 代码 · 共 57 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

PACKAGE PLUS_LIB IS 
	COMPONENT PLUSCONTROL
		PORT(CLK             :IN STD_LOGIC;
			 START,ARH,TT,EE :IN STD_LOGIC;
			 DONE,CRT,S,ENT  :OUT STD_LOGIC);
END COMPONENT; 

COMPONENT COUNT8
	PORT(CLK     :IN STD_LOGIC;
		 CRT,ENT :IN STD_LOGIC;
 		 TT      :OUT STD_LOGIC);
END COMPONENT;

COMPONENT CNT1
PORT(CLK : IN STD_LOGIC;
	 CRT :IN STD_LOGIC;
 	 OC  :OUT STD_LOGIC;
	 QA  :OUT INTEGER RANGE 0 TO 9);
END COMPONENT;

COMPONENT CNT2
PORT(CLK :IN STD_LOGIC;
	 CRT :IN STD_LOGIC;
 	 EN2 :IN STD_LOGIC;
	 EE  :OUT STD_LOGIC;
	 QB  :OUT INTEGER RANGE 0 TO 9);
END COMPONENT;

COMPONENT MUX1
PORT(BB,QB:IN INTEGER RANGE 0 TO 9;
		 S:IN STD_LOGIC;
		 B:OUT INTEGER RANGE 0 TO 9);
END COMPONENT;

COMPONENT MUX2
PORT(AA,QA :IN INTEGER RANGE 0 TO 9;
		 S :IN STD_LOGIC;
		 A :OUT INTEGER RANGE 0 TO 9);
END COMPONENT;

COMPONENT PLUS
PORT(A:IN INTEGER RANGE 0 TO 9;
	 B:IN INTEGER RANGE 0 TO 9;
	 M:OUT INTEGER RANGE 0 TO 81);
END COMPONENT;

COMPONENT TRANS
PORT(M:IN INTEGER RANGE 0 TO 81;
	 BD1,BD2:OUT INTEGER RANGE 0 TO 9);
END COMPONENT;

END PLUS_LIB;