mux1.vhd

这是一个用VHDL层次化设计的一个九九乘法表源文件,还包含仿真波形

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX1 IS
PORT(BB,QB:IN INTEGER RANGE 0 TO 9;
S:IN STD_LOGIC;
B:OUT INTEGER RANGE 0 TO 9
);
END MUX1;

ARCHITECTURE XYB OF MUX1 IS
BEGIN
   B<=QB WHEN S='1'ELSE BB;
END XYB;