plus_top.vhd

来自「这是一个用VHDL层次化设计的一个九九乘法表源文件,还包含仿真波形」· VHDL 代码 · 共 39 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.PLUS_LIB.ALL;
 
ENTITY PLUS_TOP IS
PORT(CLK:IN STD_LOGIC;
	 AA,BB: IN INTEGER RANGE 0 TO 9;
	 A,B:BUFFER INTEGER RANGE 0 TO 9;
	 EE,OC: BUFFER STD_LOGIC;
	 BD1,BD2:OUT INTEGER RANGE 0 TO 9;
	 START,ARH:IN STD_LOGIC);
END PLUS_TOP;

ARCHITECTURE XYB OF PLUS_TOP IS
SIGNAL ENT,CRT,DONE,S,TT:STD_LOGIC;
SIGNAL QA,QB,TA,TB:INTEGER RANGE 0 TO 9;
SIGNAL M: INTEGER RANGE 0 TO 81;
BEGIN
	A<=TA;
	B<=TB;
	CONTROL:PLUSCONTROL
		PORT MAP(CLK,START,ARH,TT,EE,DONE,CRT,S,ENT);
	COUNT1:COUNT8
		PORT MAP(CLK,CRT,ENT,TT);
	COUNT2:CNT1
		PORT MAP(CLK,CRT,OC,QA);
	COUNT3:CNT2
		PORT MAP(CLK,CRT,OC,EE,QB);
	M1:MUX1
		PORT MAP(BB,QB,S,TB);
	M2:MUX2
		PORT MAP(AA,QA,S,TA);
	P1:PLUS
		PORT MAP(TA,TB,M);
	P2:TRANS
		PORT MAP(M,BD1,BD2);
END XYB;