mux2.vhd

这是一个用VHDL层次化设计的一个九九乘法表源文件,还包含仿真波形

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX2 IS
PORT(AA,QA:IN INTEGER RANGE 0 TO 9;
S:IN STD_LOGIC;
A:OUT INTEGER RANGE 0 TO 9
);
END MUX2;

ARCHITECTURE XYB OF MUX2 IS
BEGIN
   A<=QA WHEN S='1'ELSE AA;
END XYB;