trans.vhd

来自「这是一个用VHDL层次化设计的一个九九乘法表源文件,还包含仿真波形」· VHDL 代码 · 共 45 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY trans IS
PORT(m:IN INTEGER RANGE 0 TO 81;
bd2,bd1:out INTEGER RANGE 0 TO 9);
END trans;

ARCHITECTURE XYB OF trans IS
BEGIN
   process(m)
begin
if m<=9 then
bd2<=0;
bd1<=m;
elsif m<=19 then
bd2<=1;
bd1<=m-10;
elsif m<=29 then
bd2<=2;
bd1<=m-20;
elsif m<=39 then
bd2<=3;
bd1<=m-30;
elsif m<=49 then
bd2<=4;
bd1<=m-40;
elsif m<=59 then
bd2<=5;
bd1<=m-50;
elsif m<=69 then
bd2<=6;
bd1<=m-60;
elsif m<=79 then
bd2<=7;
bd1<=m-70;
else
bd2<=8;
bd1<=m-80;
end if;
end process;
end xyb;