pluscontrol.vhd

来自「这是一个用VHDL层次化设计的一个九九乘法表源文件,还包含仿真波形」· VHDL 代码 · 共 49 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PLUSCONTROL IS
	PORT(CLK:IN STD_LOGIC;
		 START,ARH,TT,EE:IN STD_LOGIC;
		 DONE,CRT,S,ENT:OUT STD_LOGIC);
END PLUSCONTROL;

ARCHITECTURE XYB OF PLUSCONTROL IS
	TYPE STATE_SPACE IS(S0,S1,S2,S3);
	SIGNAL STATE:STATE_SPACE;
BEGIN
	PROCESS(CLK)
	BEGIN
		IF CLK'EVENT AND CLK='1' THEN
			CASE STATE IS
				WHEN S0=>
					IF START='1'THEN
						STATE<=S1;
					END IF;
				WHEN S1=>
					IF ARH='1'THEN
						STATE<=S3;
					ELSE
						STATE<=S2;
					END IF;
				WHEN S2=>
					IF TT='1'THEN
						STATE<=S0;
					ELSE
						STATE<=S2;
					END IF;
				WHEN S3=>
					IF EE='1'THEN
						STATE<=S1;
					END IF;
			END CASE;
		END IF;
	END PROCESS;
	DONE<='1' WHEN STATE=S0 ELSE '0';
	CRT<='0' WHEN STATE=S0 ELSE '1';
	S<='1' WHEN STATE=S3 ELSE '0';
	ENT<='1' WHEN STATE=S2 ELSE '0';
END XYB;