cnt1.vhd

来自「这是一个用VHDL层次化设计的一个九九乘法表源文件,还包含仿真波形」· VHDL 代码 · 共 34 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CNT1 IS
PORT(CLK : IN STD_LOGIC;
	 CRT:IN STD_LOGIC;
 	 OC:OUT STD_LOGIC;
	 QA:OUT INTEGER RANGE 0 TO 9);
END;

ARCHITECTURE XYB OF CNT1 IS
BEGIN
	PROCESS(CLK)
	VARIABLE COUNT:INTEGER RANGE 0 TO 9;
	BEGIN
	IF CLK'EVENT AND CLK='1' THEN
		IF CRT='1' THEN
			IF COUNT=9 THEN
				COUNT:=0;
				OC<='0';
			ELSIF COUNT=8 THEN
				COUNT:=COUNT+1;
				OC<='1';
			ELSE
				COUNT:=COUNT+1;
				OC<='0';
			END IF;
		END IF;
	END IF;
	QA<=COUNT;
	END PROCESS;
END XYB;