📄 plus_top.rpt
字号:
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 8 0 7 0 0 8 0 2 1 0 8 8 0 7 0 8 8 8 8 6 0 8 0 3 8 106/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 0 7 0 0 8 0 2 1 0 8 8 0 7 0 8 8 8 8 6 0 8 0 3 8 106/0
Device-Specific Information: d:\jiujiu\plus_top.rpt
plus_top
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
81 - - - 22 INPUT 0 0 0 1 AA0
53 - - - 20 INPUT 0 0 0 1 AA1
84 - - - -- INPUT 0 0 0 1 AA2
49 - - - 16 INPUT 0 0 0 1 AA3
2 - - - -- INPUT 0 0 0 1 ARH
79 - - - 24 INPUT 0 0 0 1 BB0
83 - - - 13 INPUT 0 0 0 1 BB1
43 - - - -- INPUT 0 0 0 1 BB2
44 - - - -- INPUT 0 0 0 1 BB3
1 - - - -- INPUT G 0 0 0 0 CLK
42 - - - -- INPUT 0 0 0 1 START
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\jiujiu\plus_top.rpt
plus_top
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
66 - - B -- OUTPUT 0 1 0 0 A0
25 - - B -- OUTPUT 0 1 0 0 A1
64 - - B -- OUTPUT 0 1 0 0 A2
51 - - - 18 OUTPUT 0 1 0 0 A3
54 - - - 21 OUTPUT 0 1 0 0 BD10
39 - - - 11 OUTPUT 0 1 0 0 BD11
35 - - - 06 OUTPUT 0 1 0 0 BD12
36 - - - 07 OUTPUT 0 1 0 0 BD13
67 - - B -- OUTPUT 0 1 0 0 BD20
8 - - - 03 OUTPUT 0 1 0 0 BD21
6 - - - 04 OUTPUT 0 1 0 0 BD22
23 - - B -- OUTPUT 0 1 0 0 BD23
22 - - B -- OUTPUT 0 1 0 0 B0
21 - - B -- OUTPUT 0 1 0 0 B1
24 - - B -- OUTPUT 0 1 0 0 B2
78 - - - 24 OUTPUT 0 1 0 0 B3
65 - - B -- OUTPUT 0 1 0 0 EE
48 - - - 15 OUTPUT 0 1 0 0 OC
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\jiujiu\plus_top.rpt
plus_top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 15 AND2 0 2 0 2 |CNT1:COUNT2|LPM_ADD_SUB:66|addcore:adder|:59
- 5 - B 16 DFFE + 0 3 1 6 |CNT1:COUNT2|:3
- 2 - B 15 DFFE + 0 3 0 3 |CNT1:COUNT2|COUNT3 (|CNT1:COUNT2|:9)
- 3 - B 15 DFFE + 0 3 0 3 |CNT1:COUNT2|COUNT2 (|CNT1:COUNT2|:10)
- 1 - B 15 DFFE + 0 3 0 3 |CNT1:COUNT2|COUNT1 (|CNT1:COUNT2|:11)
- 1 - B 16 DFFE + 0 1 0 7 |CNT1:COUNT2|COUNT0 (|CNT1:COUNT2|:12)
- 4 - B 15 OR2 s ! 0 3 0 4 |CNT1:COUNT2|~34~1
- 5 - B 15 OR2 ! 0 2 0 2 |CNT1:COUNT2|:34
- 8 - B 15 OR2 0 4 0 1 |CNT1:COUNT2|:94
- 4 - B 16 OR2 s 0 3 0 1 |CNT1:COUNT2|~144~1
- 6 - B 15 OR2 s 0 4 0 2 |CNT1:COUNT2|~150~1
- 3 - B 24 AND2 0 2 0 1 |CNT2:COUNT3|LPM_ADD_SUB:51|addcore:adder|:59
- 8 - B 24 DFFE + 0 3 1 2 |CNT2:COUNT3|:4
- 7 - B 24 DFFE + 0 3 0 3 |CNT2:COUNT3|COUNT3 (|CNT2:COUNT3|:10)
- 7 - B 16 DFFE + 0 3 0 4 |CNT2:COUNT3|COUNT2 (|CNT2:COUNT3|:11)
- 6 - B 16 DFFE + 0 3 0 5 |CNT2:COUNT3|COUNT1 (|CNT2:COUNT3|:12)
- 8 - B 16 DFFE + 0 2 0 5 |CNT2:COUNT3|COUNT0 (|CNT2:COUNT3|:13)
- 2 - B 24 OR2 ! 0 4 0 2 |CNT2:COUNT3|:35
- 4 - B 24 OR2 0 4 0 1 |CNT2:COUNT3|:111
- 3 - B 16 OR2 0 4 0 1 |CNT2:COUNT3|:117
- 5 - B 24 AND2 s 0 2 0 3 |CNT2:COUNT3|~123~1
- 2 - B 16 OR2 0 3 0 1 |CNT2:COUNT3|:123
- 5 - B 13 AND2 0 2 0 2 |COUNT8:COUNT1|LPM_ADD_SUB:39|addcore:adder|:55
- 7 - B 13 DFFE + 0 3 0 1 |COUNT8:COUNT1|:4
- 6 - B 13 DFFE + 0 2 0 1 |COUNT8:COUNT1|COUNT2 (|COUNT8:COUNT1|:6)
- 4 - B 13 DFFE + 0 2 0 1 |COUNT8:COUNT1|COUNT1 (|COUNT8:COUNT1|:7)
- 3 - B 13 DFFE + 0 1 0 2 |COUNT8:COUNT1|COUNT0 (|COUNT8:COUNT1|:8)
- 2 - B 13 AND2 0 2 0 4 |COUNT8:COUNT1|:21
- 1 - B 24 OR2 1 3 1 7 |MUX1:M1~92|:24
- 6 - B 24 OR2 1 3 1 8 |MUX1:M1~92|:30
- 1 - B 21 OR2 1 3 1 12 |MUX1:M1~92|:36
- 2 - B 21 OR2 1 3 1 8 |MUX1:M1~92|:42
- 4 - B 18 OR2 1 3 1 7 |MUX2:M2~97|:24
- 7 - B 18 OR2 1 3 1 9 |MUX2:M2~97|:30
- 8 - B 21 OR2 1 3 1 10 |MUX2:M2~97|:36
- 3 - B 21 OR2 1 3 1 8 |MUX2:M2~97|:42
- 1 - B 13 DFFE + 0 3 0 11 |PLUSCONTROL:CONTROL|STATE1 (|PLUSCONTROL:CONTROL|:10)
- 6 - B 23 DFFE + 1 2 0 12 |PLUSCONTROL:CONTROL|STATE0 (|PLUSCONTROL:CONTROL|:11)
- 7 - B 23 AND2 0 2 0 13 |PLUSCONTROL:CONTROL|:165
- 1 - B 23 OR2 1 3 0 1 |PLUSCONTROL:CONTROL|:177
- 3 - B 11 OR2 0 4 0 13 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:74
- 4 - B 17 OR2 0 4 0 4 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:84
- 6 - B 17 OR2 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:85
- 2 - B 18 OR2 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:86
- 1 - B 11 OR2 0 4 0 4 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:92
- 5 - B 17 OR2 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:165
- 8 - B 17 OR2 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:166
- 8 - B 18 OR2 0 4 0 1 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_add:sub_csa_add|csa_cell:adder0|:167
- 4 - B 11 OR2 0 4 0 7 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|:68
- 6 - B 11 OR2 s 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|~77~1
- 4 - B 19 OR2 s 0 4 0 1 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|~78~1
- 3 - B 19 OR2 0 3 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|:78
- 1 - B 19 OR2 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|:79
- 7 - B 11 AND2 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|:84
- 6 - B 18 AND2 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|:143
- 6 - B 21 AND2 s 0 4 0 1 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|~149~1
- 7 - B 21 OR2 s 0 4 0 1 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|~149~2
- 4 - B 21 OR2 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|:149
- 5 - B 19 AND2 s 0 4 0 1 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|~150~1
- 6 - B 19 OR2 s 0 4 0 1 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|~150~2
- 2 - B 19 OR2 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|csa_cell:adder0|:150
- 7 - B 17 OR2 0 4 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry4
- 2 - B 17 OR2 0 3 0 1 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|pcarry5
- 1 - B 08 OR2 0 2 0 14 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:126
- 3 - B 17 OR2 0 4 0 6 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:127
- 1 - B 17 OR2 0 3 0 5 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:128
- 1 - B 18 OR2 0 4 0 6 |PLUS:P1|LPM_MULT:24|multcore:mult_core|csa_add:padder|lpm_add_sub:cpa_adder|addcore:adder|:129
- 5 - B 18 AND2 0 2 0 2 |PLUS:P1|LPM_MULT:24|multcore:mult_core|decoder_node2_3
- 3 - B 18 AND2 0 2 0 1 |PLUS:P1|LPM_MULT:24|multcore:mult_core|decoder_node3_2
- 2 - B 11 AND2 0 2 0 4 |TRANS:P2|LPM_ADD_SUB:634|addcore:adder|:125
- 1 - B 09 OR2 0 4 0 5 |TRANS:P2|:159
- 5 - B 11 OR2 0 2 0 4 |TRANS:P2|:179
- 7 - B 12 OR2 s ! 0 2 0 2 |TRANS:P2|~199~1
- 1 - B 12 OR2 ! 0 4 0 5 |TRANS:P2|:199
- 2 - B 12 OR2 0 4 0 4 |TRANS:P2|:239
- 3 - B 12 OR2 ! 0 4 0 4 |TRANS:P2|:279
- 5 - B 12 OR2 0 4 0 4 |TRANS:P2|:319
- 8 - B 12 OR2 s 0 2 0 2 |TRANS:P2|~321~1
- 4 - B 12 OR2 ! 0 4 0 4 |TRANS:P2|:359
- 2 - B 01 OR2 0 4 0 4 |TRANS:P2|:401
- 6 - B 12 AND2 ! 0 2 0 5 |TRANS:P2|:444
- 4 - B 06 AND2 0 2 1 2 |TRANS:P2|:939
- 6 - B 03 OR2 s ! 0 2 0 2 |TRANS:P2|~966~1
- 4 - B 03 AND2 0 4 1 0 |TRANS:P2|:966
- 7 - B 03 AND2 0 3 0 1 |TRANS:P2|:984
- 2 - B 03 OR2 0 4 1 0 |TRANS:P2|:993
- 3 - B 03 OR2 0 3 0 1 |TRANS:P2|:1003
- 5 - B 03 OR2 0 3 0 1 |TRANS:P2|:1009
- 1 - B 03 OR2 0 4 1 1 |TRANS:P2|:1020
- 3 - B 01 OR2 0 4 0 1 |TRANS:P2|:1024
- 4 - B 01 OR2 0 4 0 1 |TRANS:P2|:1027
- 5 - B 01 OR2 0 4 0 1 |TRANS:P2|:1030
- 6 - B 01 OR2 0 3 0 1 |TRANS:P2|:1033
- 7 - B 01 OR2 0 4 0 1 |TRANS:P2|:1036
- 8 - B 01 OR2 0 4 0 1 |TRANS:P2|:1039
- 1 - B 01 OR2 0 4 0 1 |TRANS:P2|:1042
- 2 - B 08 OR2 0 4 1 0 |TRANS:P2|:1045
- 2 - B 06 OR2 0 4 0 1 |TRANS:P2|:1054
- 3 - B 06 OR2 0 4 0 1 |TRANS:P2|:1057
- 5 - B 06 OR2 0 3 0 1 |TRANS:P2|:1060
- 6 - B 06 OR2 0 4 0 1 |TRANS:P2|:1063
- 7 - B 06 OR2 0 3 0 1 |TRANS:P2|:1066
- 8 - B 06 OR2 0 4 0 1 |TRANS:P2|:1069
- 1 - B 06 OR2 0 3 1 0 |TRANS:P2|:1072
- 8 - B 11 OR2 0 2 1 0 |TRANS:P2|:1099
- 5 - B 21 AND2 0 2 1 0 |TRANS:P2|:1126
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\jiujiu\plus_top.rpt
plus_top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 21/ 96( 21%) 14/ 48( 29%) 24/ 48( 50%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\jiujiu\plus_top.rpt
plus_top
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 16 CLK
Device-Specific Information: d:\jiujiu\plus_top.rpt
plus_top
** EQUATIONS **
AA0 : INPUT;
AA1 : INPUT;
AA2 : INPUT;
AA3 : INPUT;
ARH : INPUT;
BB0 : INPUT;
BB1 : INPUT;
BB2 : INPUT;
BB3 : INPUT;
CLK : INPUT;
START : INPUT;
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