traffic_control.rpt

该程序是用一片HDPLD和若干外围电路实现的十字路口交通控制器,其中包含顶层图形文件和源文件以及仿真波形

traffic_control

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (37)    21    B       TFFE   +  t        0      0   0    3    2    9    1  state~2


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                    d:\project\traffic_control.rpt
traffic_control

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                             Logic cells placed in LAB 'B'
        +------------------- LC25 c1
        | +----------------- LC26 c2
        | | +--------------- LC18 c3
        | | | +------------- LC19 g1
        | | | | +----------- LC20 g2
        | | | | | +--------- LC17 r1
        | | | | | | +------- LC24 r2
        | | | | | | | +----- LC21 state~2
        | | | | | | | | +--- LC23 y1
        | | | | | | | | | +- LC22 y2
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> * * * * * * * * * * | - * | <-- r1
LC21 -> * * * * * * * * * * | - * | <-- state~2

Pin
43   -> - - - - - - - - - - | - - | <-- clk
7    -> - - - - - * * * - - | - * | <-- reset
6    -> - - - - - - - * - - | - * | <-- w1
5    -> - - - - - * * - - - | - * | <-- w2
4    -> - - - - - - - * - - | - * | <-- w3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                    d:\project\traffic_control.rpt
traffic_control

** EQUATIONS **

clk      : INPUT;
reset    : INPUT;
w1       : INPUT;
w2       : INPUT;
w3       : INPUT;

-- Node name is 'c1' 
-- Equation name is 'c1', location is LC025, type is output.
 c1      = LCELL( _EQ001 $  GND);
  _EQ001 =  r1 & !state~2;

-- Node name is 'c2' 
-- Equation name is 'c2', location is LC026, type is output.
 c2      = LCELL(!r1 $  state~2);

-- Node name is 'c3' 
-- Equation name is 'c3', location is LC018, type is output.
 c3      = LCELL( _EQ002 $  GND);
  _EQ002 = !r1 &  state~2;

-- Node name is 'g1' 
-- Equation name is 'g1', location is LC019, type is output.
 g1      = LCELL( _EQ003 $  GND);
  _EQ003 = !r1 &  state~2;

-- Node name is 'g2' 
-- Equation name is 'g2', location is LC020, type is output.
 g2      = LCELL( _EQ004 $  GND);
  _EQ004 =  r1 & !state~2;

-- Node name is 'r1' = 'state~1' 
-- Equation name is 'r1', location is LC017, type is output.
r1       = _LC017~NOT;
_LC017~NOT = DFFE( _EQ005 $  VCC, GLOBAL( clk),  VCC, !reset,  VCC);
  _EQ005 = !reset &  state~2 &  w2
         # !reset & !r1 & !w2;

-- Node name is 'r2' = 'state~1~1' 
-- Equation name is 'r2', location is LC024, type is output.
 r2      = DFFE( _EQ006 $  GND, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ006 = !reset &  state~2 &  w2
         # !reset & !r1 & !w2;

-- Node name is 'state~2' 
-- Equation name is 'state~2', location is LC021, type is buried.
state~2  = TFFE( _EQ007, GLOBAL( clk), !reset,  VCC,  VCC);
  _EQ007 = !reset &  r1 & !state~2 &  w1
         # !r1 &  state~2 &  w3
         #  reset &  state~2;

-- Node name is 'y1' 
-- Equation name is 'y1', location is LC023, type is output.
 y1      = LCELL( _EQ008 $  GND);
  _EQ008 = !r1 & !state~2;

-- Node name is 'y2' 
-- Equation name is 'y2', location is LC022, type is output.
 y2      = LCELL( _EQ009 $  GND);
  _EQ009 =  r1 &  state~2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                             d:\project\traffic_control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,009K