📄 count05.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY count05 IS
PORT(
clk:IN STD_LOGIC;
enable:IN STD_LOGIC;
c:OUT STD_LOGIC);
END count05;
ARCHITECTURE arc_count05 OF count05 IS
BEGIN
PROCESS(clk)
VARIABLE cnt:INTEGER RANGE 5 DOWNTO 0;
BEGIN
IF (clk 'EVENT AND clk = '1') THEN
IF enable = '1' AND cnt < 5 THEN
cnt := cnt + 1;
ELSE
cnt := 0;
END IF;
END IF;
IF cnt = 5 THEN
C <= '1';
ELSE
C <= '0';
END IF;
END PROCESS;
END arc_count05;
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