traffic.rpt
来自「该程序是用一片HDPLD和若干外围电路实现的十字路口交通控制器,其中包含顶层图形」· RPT 代码 · 共 740 行 · 第 1/3 页
RPT
740 行
Total: 0 7 0 0 0 0 8 0 8 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 31/0
Device-Specific Information: d:\project\traffic.rpt
traffic
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 clk
28 - - C -- INPUT 0 0 0 4 reset
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\project\traffic.rpt
traffic
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
17 - - A -- OUTPUT 0 1 0 0 g1
21 - - B -- OUTPUT 0 1 0 0 g2
18 - - A -- OUTPUT 0 1 0 0 r1
22 - - B -- OUTPUT 0 1 0 0 r2
19 - - A -- OUTPUT 0 1 0 0 y1
23 - - B -- OUTPUT 0 1 0 0 y2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\project\traffic.rpt
traffic
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 07 DFFE + 0 3 0 6 |COUNT05:3|cnt2 (|COUNT05:3|:4)
- 3 - B 07 DFFE + 0 3 0 6 |COUNT05:3|cnt1 (|COUNT05:3|:5)
- 7 - B 07 DFFE + 0 3 0 6 |COUNT05:3|cnt0 (|COUNT05:3|:6)
- 2 - B 09 AND2 0 3 0 2 |COUNT26:2|LPM_ADD_SUB:56|addcore:adder|:67
- 5 - B 09 DFFE + 0 3 0 2 |COUNT26:2|cnt4 (|COUNT26:2|:4)
- 4 - B 09 DFFE + 0 2 0 3 |COUNT26:2|cnt3 (|COUNT26:2|:5)
- 6 - B 09 DFFE + 0 3 0 3 |COUNT26:2|cnt2 (|COUNT26:2|:6)
- 7 - B 09 DFFE + 0 2 0 4 |COUNT26:2|cnt1 (|COUNT26:2|:7)
- 5 - B 02 DFFE + 0 1 0 5 |COUNT26:2|cnt0 (|COUNT26:2|:8)
- 3 - B 09 OR2 s 0 2 0 1 |COUNT26:2|~22~1
- 1 - B 09 OR2 0 4 0 5 |COUNT26:2|:44
- 8 - B 09 OR2 s ! 0 4 0 2 |COUNT26:2|~103~1
- 6 - B 12 AND2 0 3 0 2 |COUNT30:4|LPM_ADD_SUB:56|addcore:adder|:67
- 8 - B 12 DFFE + 0 3 0 1 |COUNT30:4|cnt4 (|COUNT30:4|:4)
- 7 - B 12 DFFE + 0 2 0 2 |COUNT30:4|cnt3 (|COUNT30:4|:5)
- 5 - B 12 DFFE + 0 3 0 2 |COUNT30:4|cnt2 (|COUNT30:4|:6)
- 3 - B 12 DFFE + 0 3 0 3 |COUNT30:4|cnt1 (|COUNT30:4|:7)
- 1 - B 12 DFFE + 0 2 0 5 |COUNT30:4|cnt0 (|COUNT30:4|:8)
- 2 - B 12 OR2 0 4 0 5 |COUNT30:4|:22
- 4 - B 12 AND2 0 2 0 3 |COUNT30:4|:44
- 6 - B 02 DFFE + 1 4 1 4 |TRAFFIC_CONTROL:1|state~1
- 2 - B 02 DFFE + 1 3 1 3 |TRAFFIC_CONTROL:1|state~2
- 3 - B 02 DFFE + 1 4 1 4 |TRAFFIC_CONTROL:1|state~3
- 4 - B 02 DFFE + 1 3 1 5 |TRAFFIC_CONTROL:1|state~4
- 4 - B 07 OR2 0 4 0 1 |TRAFFIC_CONTROL:1|:88
- 8 - B 07 AND2 0 4 0 1 |TRAFFIC_CONTROL:1|:90
- 6 - B 07 OR2 ! 0 4 0 1 |TRAFFIC_CONTROL:1|:96
- 5 - B 07 OR2 0 4 0 1 |TRAFFIC_CONTROL:1|:98
- 1 - B 07 OR2 0 2 0 3 |TRAFFIC_CONTROL:1|:142
- 8 - B 02 OR2 0 2 1 0 |TRAFFIC_CONTROL:1|:174
- 1 - B 02 OR2 0 2 1 0 |TRAFFIC_CONTROL:1|:220
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\project\traffic.rpt
traffic
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 2/ 96( 2%) 14/ 48( 29%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\project\traffic.rpt
traffic
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 17 clk
Device-Specific Information: d:\project\traffic.rpt
traffic
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 reset
Device-Specific Information: d:\project\traffic.rpt
traffic
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is 'g1'
-- Equation name is 'g1', type is output
g1 = _LC2_B2;
-- Node name is 'g2'
-- Equation name is 'g2', type is output
g2 = !_LC4_B2;
-- Node name is 'r1'
-- Equation name is 'r1', type is output
r1 = _LC8_B2;
-- Node name is 'r2'
-- Equation name is 'r2', type is output
r2 = _LC1_B2;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC6_B2;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC3_B2;
-- Node name is '|COUNT05:3|:6' = '|COUNT05:3|cnt0'
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC1_B7 & !_LC3_B7 & !_LC7_B7
# _LC1_B7 & !_LC2_B7 & !_LC7_B7;
-- Node name is '|COUNT05:3|:5' = '|COUNT05:3|cnt1'
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC1_B7 & !_LC2_B7 & !_LC3_B7 & _LC7_B7
# _LC1_B7 & !_LC2_B7 & _LC3_B7 & !_LC7_B7;
-- Node name is '|COUNT05:3|:4' = '|COUNT05:3|cnt2'
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC1_B7 & _LC2_B7 & !_LC3_B7 & !_LC7_B7
# _LC1_B7 & !_LC2_B7 & _LC3_B7 & _LC7_B7;
-- Node name is '|COUNT26:2|:8' = '|COUNT26:2|cnt0'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC1_B9 & !_LC5_B2;
-- Node name is '|COUNT26:2|:7' = '|COUNT26:2|cnt1'
-- Equation name is '_LC7_B9', type is buried
_LC7_B9 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC1_B9 & _LC5_B2 & !_LC7_B9
# _LC1_B9 & !_LC5_B2 & _LC7_B9;
-- Node name is '|COUNT26:2|:6' = '|COUNT26:2|cnt2'
-- Equation name is '_LC6_B9', type is buried
_LC6_B9 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC1_B9 & !_LC5_B2 & _LC6_B9
# _LC1_B9 & _LC6_B9 & !_LC7_B9
# _LC1_B9 & _LC5_B2 & !_LC6_B9 & _LC7_B9;
-- Node name is '|COUNT26:2|:5' = '|COUNT26:2|cnt3'
-- Equation name is '_LC4_B9', type is buried
_LC4_B9 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC1_B9 & !_LC2_B9 & _LC4_B9
# _LC1_B9 & _LC2_B9 & !_LC4_B9;
-- Node name is '|COUNT26:2|:4' = '|COUNT26:2|cnt4'
-- Equation name is '_LC5_B9', type is buried
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?